ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 104

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
EDID Data structure mapping: An internal
address pointer defines the memory location being
addressed. It is made of two 8-bit registers AHR
and ALR.
AHR is initialized by software. It defines the 256-
byte block within the 64K address space
containing the data structure.
ALR is loaded with the data address sent by the
master after a write Device Address. It defines the
Figure 64. Mapping of DDC2B data structure
104/144
FFFFh
0000h
FFFFh
0000h
Addr Pointer
128-byte Data
128-byte Data
Basic EDID v1
Structure
Basic EDID v1
Structure
A0h/A1h
A0h/A1h
15
AHR<7:1>
Addr Pointer
DDC v2 / P&D / FPDI-2 modes: CF[1:0] bits != 10b
ALR :
00h -> 7Fh
ALR :
00h -> 7Fh
DDC v2 + P&D mode: CF[1:0] bits = 10b
9
8
1
15
7
FFFFh
FFFFh
0000h
0000h
Extended EDID v1 (if present)
Extended EDID v1 (if present)
AHR
ALR
128-byte Data
128-byte Data
A0h/A1h
Structure
A0h/A1h
Structure
8
0
7
Addr Pointer
byte within the data structure currently addressed.
ALR is reset upon entry into the DDC2B mode.
One exception to this arrangement is when the
CF[1:0] bits = 10b. In this case the two EDID
versions
addresses. The LSB of AHR is therefore ignored
and automatically set to 1 to address the 128-byte
EDID and set to 0 to address its 256-byte
counterpart (see
ALR
80h -> FFh
ALR :
ALR :
80h -> FFh
0
15
must
AHR<7:1>
FFFFh
FFFFh
0000h
0000h
Figure
A2h/A3h + A6h/A7h
coexist
256-byte Data
256-byte Data
EDID v2
A2h/A3h
9
Structure
Structure
EDID v2
64).
8
0
7
at
ALR
non-overlapping
AHR<7:1>
AHR
ALR
ALR
256
*
512
*
0