ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 127

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST7 ADDRESSING MODES (Cont’d)
5.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required
information for the CPU to process the operation.
5.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte
contains the operand value.
NOP
TRAP
WFI
HALT
RET
IRET
SIM
RIM
SCF
RCF
RSP
LD
CLR
PUSH/POP
INC/DEC
TNZ
CPL, NEG
MUL
SLL, SRL, SRA, RLC,
RRC
SWAP
LD
CP
BCP
AND, OR, XOR
ADC, ADD, SUB, SBC
Immediate Instruction
Inherent Instruction
No operation
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
Disabled, forces a RESET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
Reset Carry Flag
Reset Stack Pointer
Load
Clear
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Shift and Rotate Operations
Swap Nibbles
Load
Compare
Bit Compare
Logical Operations
Arithmetic Operations
Function
Function
5.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte
addressing space, but requires 2 bytes after the
opcode.
5.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte
after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte
addressing space and requires 2 bytes after the
opcode.
5.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory
(pointer).
The pointer address follows the opcode. The
indirect addressing mode consists of two sub-
modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
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