ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 45

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index, i , may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free
running counter after a transition detected by the
ICAP i pin (see figure 5).
IC i Rregister is a read-only register.
The active transition is software programmable
through the IEDG i bit of the Control Register (CR i ).
Timing resolution is one count of the free running
counter: (
Procedure
To use the input capture function select the
following in the CR2 register:
– Select the timer clock (CC1-CC0) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
Clock Control
ICAP2 pin with the IEDG2 bit.
input capture.
IC i R
f
CPU/(CC1.CC0)
Bits).
MS Byte
IC i HR
).
LS Byte
IC i LR
Table 15
– Select the edge of the active transition on the
When an input capture occurs:
– ICF i bit is set.
– The IC i R register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICF i bit is set.
2. An access (read or write) to the IC i LR register.
After reading the IC i HR register, transfer of input
capture data is inhibited until the IC i LR register is
also read.
The IC i R register always contains the free running
counter value which corresponds to the most
recent input capture.
ICAP1 pin with the IEDG1 bit.
running counter on the active transition on the
ICAP i pin (see
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
ST72774/ST727754/ST72734
Figure
32).
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