ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 75

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.5 TIMING MEASUREMENT UNIT (TMU)
4.5.1 Introduction
The timing measurement unit (TMU) allows the
analysis of the current video timing characteristics
in order to control display position and size.
It consists of measuring the timing between the
horizontal or vertical sync output signals and the
active video signal input (AV).
4.5.2 Main Features
4.5.3 Functional Description
The Timing Measurement Unit is centered around
an 11-bit counter. Depending on the H_V bit of the
control register, the TMU measures the horizontal
or vertical video characteristics.
Figure 47. TMU Block Diagram
Horizontal or vertical timing measurement
Oscillator clock f
horizontal measurement
Horizontal sync signal (HSYNCO or HFBACK)
and Vertical sync signal (VSYNCO or VFBACK)
used for all measurements
Measurements performed on positive signals
only
11-bit counter
Overflow detection
Note 1: Selection between Sync outputs or Flyback inputs is made in MISCR register (bit 6: FLY_SYN)
T1[7:0]
TMUT1CR
8
(FROM SYNC PROCESSOR)
OSC
(24 or 12 MHz) used for
11 bit COUNTER
COMPARATOR
T2[7:0]
TMUT2CR
11
8
VSYNCO or VFBACK
HSYNCO or HFBACK
ST7 INTERNAL BUS
T2[10]
For horizontal analysis (refer to
Note: Horizontal measurement is inhibited during the high
For vertical analysis (refer to
T2[9] T2[8]
– Obtain the minimum number of oscillator clock
– Obtain the minimum number of oscillator clock
– Obtain the minimum number of horizontal
cycles (H1) between the falling edge of the
horizontal sync signal (HSYNCO or HFBACK)
and the first rising edge of the active video in-
put (AV), for all lines, between 2 consecutive
vertical sync pulses.
cycles (H2) between the last falling edge of
the active video input (AV) and the rising edge
of the horizontal sync signal (HSYNCO or HF-
BACK) for all lines, between 2 consecutive
vertical sync pulses.
sync pulses (V1) between the falling edge of
the vertical sync signal (VSYNCO or VF-
BACK) and the first rising edge of the active
video input, during 2 consecutive frames.
3
level of VSYNCO or VFLYBACK.
f
OSC
Clock
(1)
(1)
Start
Stop
SUP
T1[10]
ST72774/ST727754/ST72734
T1[9] T1[8]
3
CONTROL
Figure
H_V
Figure
TMUCSR
49):
START
48):
AV
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