ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 124

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
4.10.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the
result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
conversion result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
4.10.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in
While the ADC is on, these two phases are
continuously repeated.
At the end of each conversion, the sample
capacitor is kept loaded with the previous
measurement load. The advantage of this
behaviour is that it minimizes the current
consumption on the analog pin in case of single
input channel measurement.
4.10.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in
definitions and to
124/144
SSA
AIN
Sample capacitor loading [duration: t
During this phase, the V
measured is loaded into the C
capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the C
from the analog input pin to get the optimum
analog to digital conversion accuracy.
DDA
is the maximum recommended impedance
(low-level voltage reference) then the
(high-level voltage reference) then the
ADC
sample capacitor is disconnected
Figure 77
AIN
Section 4.10.6
Figure
AIN
) is lower than or equal to
) is greater than or equal
AIN
77:
for the timings.
CONV
input voltage to be
]
ADC
for the bit
LOAD
sample
]
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
The analog input ports must be configured as
input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
ADC Conversion
In the CSR register:
When a conversion is complete
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 77. ADC Conversion Timings
4.10.4 Low Power Mode
Note: The A/D converter is disabled by resetting the
4.10.5 Interrupts
None
WAIT
ADON
HOLD
CONTROL
– Select the CH[3:0] bits to assign the analog
– Set the ADON bit to enable the A/D converter
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
Mode
channel to be converted.
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
valid until the next conversion has ended.
ADON bit. With this feature, power consumption is
reduced when no conversion is needed and be-
tween single shot conversions.
t
LOAD
No effect on A/D Converter
t
CONV
ADC
=4/f
COCO BIT SET
Description
CPU
).
ADCCSR WRITE
OPERATION