ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 70

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
COUNTER CONTROL REGISTER (CCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = PSCD Prescaler Enable bit.
Bit 6:5 = LCV1, LCV0 VSYNCO Extraction Control
Bit 4:0 = CV4-CV0 Counter Captured Value.
These bits contain the counter captured value in
different modes.
In VSYNCO extraction mode, they contain the
HSYNCI pulse-width measurement.
POLARITY REGISTER (POLR)
Bits 5-4 Read Only, other bits Read/Write
Reset Value: 0000 1000 (08h)
Bit 7 = SOG Sync On Green Detector
SOG is set by hardware if CSYNCI pulse is not
included in the window between HSYNCI rising
edge and HSYNCI falling edge + dt .
Cleared by software.
70/144
SOG
PSCD
LCV1
7
0: Enable the Prescaler by 256
1: Disable the Prescaler and reset it to 7Fh. This
0
0
1
1
7
also disables the ICAP2 event.
0
LCV0
LCV1
VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV
0
1
0
1
Counter capture on input falling edge
CV4-0 = counter maximum threshold
Counter capture on input rising edge
CV4-0 = counter minimum threshold
LCV0 CV4 CV3 CV2 CV1 CV0
CSYNCI/HSYNCI Negative polarity
CSYNCI/HSYNCI Positive polarity
VSYNC0 Control Bits
Extraction mode
Extraction mode
Normal mode
Normal mode
0
0
Table 19. Sync On Green Window
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 = VPOL Vertical Sync polarity (read only)
Note: If the Vertical Sync polarity is changing, the VPOL
Bit 4 = 2FHDET Detection of Pre/Post Equalization
pulses (read only).
This bit is continuously updated by hardware. It is
valid when the sync generator and horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0).
Bit 3 = HVSEL Alternate Sync Input Select.
This bit selects between the two sets of Horizontal
and Vertical Sync inputs
Bit 2 = VCORDIS Extension Disable Signal
(Extension with VGENR Register)
Bit 1 = CLPINV Programmable ClampOut pulse
polarity.
Bit 0 = BLKINV Programmable blanking polarity
0: Positive polarity
1: Negative polarity
0: None detected
1: Pre/Post Equalization pulses detected
0: HSYNCI2 / VSYNCI2
1: HSYNCI1 / VSYNCI1
0: enable
1: disable
0: Positive
1: Negative
0: Negative
1: Positive
WINDOW DELAY
bit will be updated after a typical delay of 4 msec.
dt
165 ns
min.
250 ns
max.