ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 80

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
USB INTERFACE (Cont’d)
4.6.4 Register Description
DMA ADDRESS REGISTER (DMAR)
Read / Write
Reset Value: Undefined
Bits 7:0=DA[15:8] DMA address bits 15-8.
See the description of bits DA7-6 in the next
register (IDR).
INTERRUPT/DMA REGISTER (IDR)
Read / Write
Reset Value: xxxx 0000 (x0h)
Figure 51. DMA buffers
80/144
DA15
DA7
7
7
DA14
DA6
DA13
EP1
DA15-6,000000
DA12
EP0
DA11
CNT3
CNT2
DA10
CNT1
DA9
CNT0
DA8
0
0
101111
101000
100111
100000
011111
011000
010111
010000
001111
001000
000111
000000
Bits 7:6 = DA[7:6] DMA address bits 7-6.
The software must write the start address of the
DMA memory area whose most significant bits are
given by DA15-DA6. The remaining 6 address bits
are set by hardware. See
Bits 5:4 = EP[1:0] Endpoint number (read-only).
These bits identify the endpoint which required
attention.
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
Endpoint 2 RX
Endpoint 1 RX
Endpoint 0 RX
Endpoint 2 TX
Endpoint 1 TX
Endpoint 0 TX
Figure
51.