ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 59

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

SYNC PROCESSOR (SYNC) (Cont’d)
ClampOut and Moire Signal
Clamp Output signal
The clamping pulse generator can control the
pulse width and polarity signal and can be
configured as pseudo-front porch or back porch.
To use the ClampOut signal:
– Select the Clamping Pulse width:
– Program the Clamp polarity:
– Select the ClampOut signal as back-porch (after
– Enable the CLAMPOUT signal:
Figure 40. Clamping Pulse (CLAMPOUT) Delay
falling edge of HSYNCO) or pseudo-front porch
(after the rising edge of HSYNCO):
CLMPEN bit in ENR register
CLPINV bit in POLR register
BP0/BP1 bits in MCR register
HS0/HS1 bits in MCR register.
HSYNCO
CLAMPOUT
Programmable clamping width: 0, 167ns, 333ns, 666ns
Maximum delay:
(Fixed delay of 10 to 30ns) + (f
-
Moire Signal
The Moire output signal is available (instead of the
clamping signal) to reduce the screen Moire effect
and improve color transitions.
The CLAMPOUT pin is alternatively used to output
a Moire signal.
The output signal toggles at each HFBACK rising
edge. After each VFBACK falling edge, the value
of the Moire output is the opposite of the previous
one, independent of the number of HFBACK
pulses during the VFBACK low level.
To use the Moire signal:
– Select the Moire signal:
– Enable the output signal:
Reset the BP0/BP1 bits in MCR register
CLMPEN bit in ENR register
OSC
/2) = approx. 110ns.
ST72774/ST727754/ST72734
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