ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 116

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
4.9 PWM/BRM GENERATOR (DAC)
4.9.1 Introduction
This PWM/BRM peripheral includes two types of
PWM/BRM outputs, with differing step resolutions
based on the Pulse Width Modulator (PWM) and
Binary Rate Multiplier (BRM) Generator technique
are available. It allows the digital to analog
conversion (DAC) when used with external
filtering.
4.9.2 Main Features
4.9.3 Functional Description
4.9.3.1 PWM/BRM
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator
consists of a 12-bit counter (common for all
channels), a comparator and the PWM/BRM
generation logic.
Figure 69. PWM Generation
116/144
Fixed frequency: f
Resolution: T
10-Bit PWM/BRM generator with a step of
V
DD
PWM OUTPUT
/2
COUNTER
COMPARE
10
VALUE
(5mV if V
000
63
CPU
DD
CPU
OVERFLOW
=5V)
/64
T
CPU
x 64
PWM Generation
The counter increments continuously, clocked at
internal CPU clock. Whenever the 6 least
significant bits of the counter (defined as the PWM
counter) overflow, the output level for all active
channels is set.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
This Pulse Width modulated signal must be
filtered, using an external RC network placed as
close as possible to the associated pin. This
provides an analog voltage proportional to the
average charge passed to the external capacitor.
Thus for a higher mark/space ratio (High time
much greater than Low time) the average output
voltage is higher. The external components of the
RC network should be selected for the filtering
level required for control of the system variable.
Each output may individually have its polarity
inverted by software, and can also be used as a
logical output.
OVERFLOW
OVERFLOW
t
t