PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 93

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2
15.3
15.3.1
15.3.2
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C7300A complies with the ordering
rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table
summarizes the ordering relationship of all the transactions through the bridge.
PMW - Posted write (either memory write or memory write & invalidate)
DRR - Delayed read request (all memory read, I/O read & configuration read)
DWR - Delayed write request (I/O write & configuration write, memory write to
DRC - Delayed read completion (all memory read, I/O read & configuration read)
DWC - Delayed write completion (I/O write & configuration write, memory write
Cycle type shown on each row is the subsequent cycle after the previous shown on the
column.
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must
complete on the target bus in the order in which they were received in the initiator bus.
In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous
PMW heading to the same direction must be completed before the DRR can be attempted
on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the
head of the delayed transaction queue.
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
MASTER ABORT
Master abort indicates that when PI7C7300A acts as a master and receives no response
(i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the
bridge deasserts FRAME# and then deasserts IRDY#.
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number of‘1’s) across
AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are
Can Row Pass Column?
PMW (Row 1)
DRR (Row 2)
DWR (Row 3)
DRC (Row 4)
DWC (Row 5)
certain location)
to ccertain location
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PMW
Column 1
No
No
No
No
Yes
DRR
Column 2
No
Yes
Yes
No
Yes
DWR
Column 3
Yes
No
No
Yes
Yes
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
DRC
Column 4
Yes
Yes
Yes
No
No
PI7C7300A
DWC
Column 5
Yes
Yes
Yes
No
No