PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 80

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PI7C7300ANAE

Manufacturer Part Number
PI7C7300ANAE
Description
IC PCI-PCI BRIDGE 3PORT 272-BGA
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C7300ANAE

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
272-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C7300ANAE
Manufacturer:
Pericom
Quantity:
10 000
14.1.24
14.1.25
14.1.26
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
ECP POINTER REGISTER – OFFSET 34h
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
31:0
Bit
7:0
Bit
16
17
18
I/O Limit
Function
Address, Upper
16-bits [31:16]
Function
Enhanced
Capabilities Port
Pointer
Function
Parity Error
Response
S1_SERR#
enable
ISA enable
Type
R/W
Type
R/O
Type
R/W
R/W
R/W
Page 80 OF 109
Description
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
Description
Enhanced capabilities port offset pointer. Read as B0h to indicate
that the first item resides at that configuration offset.
Description
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
Controls the forwarding of S1_SERR# or S2_SERR# to the primary
interface.
0: disable the forwarding of S1_SERR# or S2_SERR# to primary
interface
1: enable the forwarding of S1_SERR# or S2_SERR# to primary
interface
Reset to 0
Modifies the bridge’s response to ISA I/O addresses, applying only to
those addresses falling within the I/O base and limit address registers
and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the last
768 bytes in each 1KB block
Reset to 0
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A

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