PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 63

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.2
8.3
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C7300A ignores upstream lock and transactions. PI7C7300A will pass these
transactions as normal transactions without lock established.
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C7300A must
maintain the lock on the target bus for any subsequent locked transactions until the
initiator relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction
of a locked sequence. On subsequent transactions in the sequence, the target retry has no
effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock.
PI7C7300A does not know whether the current transaction is the last one in a sequence
of locked transactions until the initiator de-asserts the LOCK# signal at end of the
transaction.
When the last locked transaction is a delayed transaction, PI7C7300A has already
completed the transaction on the target bus. In this example, as soon as PI7C7300A
detects that the initiator has relinquished the LOCK# signal by sampling it in the de-
asserted state while FRAME# is deasserted, PI7C7300A de-asserts the LOCK# signal on
the target bus as soon as possible. Because of this behavior, LOCK# may not be de-
asserted until several cycles after the last locked transaction has been completed on the
target bus. As soon as PI7C7300A has de-asserted LOCK# to indicate the end of a
sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C7300A de-asserts
LOCK# on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C7300A receives a target abort or a master abort in response to a locked
delayed transaction, PI7C7300A returns a target abort or a master abort when the initiator
repeats the locked transaction. The initiator must then deassert LOCK# at the end of the
transaction. PI7C7300A sets the appropriate status bits, flagging the abnormal target
termination condition (see Section 4.8). Normal forwarding of unlocked posted and
delayed transactions is resumed.
When PI7C7300A receives a target abort or a master abort in response to a locked posted
write transaction, PI7C7300A cannot pass back that status to the initiator. PI7C7300A
asserts SERR# on the initiator bus when a target abort or a master abort is received
during a locked posted write transaction, if the SERR# enable bit is set in the command
register. Signal SERR# is asserted for the master abort condition if the master abort mode
bit is set in the bridge control register (see Section 7.4).
Page 63 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A