PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 13

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
3.2
SIGNAL DEFINITIONS
SIGNAL TYPES
PRIMARY BUS INTERFACE SIGNALS
Signal Type
PI
PIU
PID
PO
PB
PSTS
PTS
POD
Name
P_AD[31:0]
P_CBE[3:0]
P_PAR
P_FRAME#
Pin #
Y7, W7, Y8, W8,
V8, U8, Y9, W9,
W10, V10, Y11,
V11, U11, Y12,
W12, V12, V16,
W16, Y16, W17,
Y17, U18, W18,
Y18, U19, W19,
Y19, U20, V20,
Y20, T17, R17
V9, U12, U16,
V19
U15
W13
Description
PCI input (3.3V, 5V tolerant)
PCI input (3.3V, 5V tolerant) with weak pull-up
PCI input (3.3V, 5V tolerant) with weak pull-down
PCI output (3.3V)
PCI tri-state bidirectional (3.3V, 5V tolerant)
PCI sustained tri-state bi-directional (Active LOW signal which must be driven
inactive for one cycle before being tri-stated to ensure HIGH performance on a
shared signal line)
PCI tri-state output
PCI output which either drives LOW (active state) or tri-state
Page 13 OF 109
Type
PB
PB
PB
PSTS
Description
Primary Address/Data. Multiplexed address and data
bus. Address is indicated by P_FRAME# assertion.
Write data is stable and valid when P_IRDY# is
asserted and read data is stable and valid when
P_TRDY# is asserted. Data is transferred on rising
clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C7300A drives P_AD to
a valid logic level when P_GNT# is asserted.
Primary Command/Byte Enables. Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C7300A drives
P_CBE[3:0] to a valid logic level when P_GNT# is
asserted.
Primary Parity. Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle
after the address phase (indicated by assertion of
P_FRAME#) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY# is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY# is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C7300A
drives P_PAR to a valid logic level when P_GNT# is
asserted.
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME#
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted
state for one cycle.
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A