PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 75

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.5
14.1.6
14.1.7
14.1.8
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFEST 08h
CACHE LINE SIZE REGISTER – OFFSET 0Ch
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
27
28
29
30
31
Bit
7:0
Bit
15:8
23:16
31:24
Bit
7:0
Bit
15:8
Received Target
Received Master
Signaled System
Detected Parity
Sub-Class Code
Base Class Code
Cache Line Size
Primary Latency
Function
Signaled Target
Abort
Abort
Abort
Error
Error
Function
Revision
Function
Programming
Interface
Function
Function
timer
Type
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
Type
R/O
R/O
R/O
Type
R/W
Type
R/W
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Description
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
Set to 1 when P_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
Description
Indicates revision number of device. Hardwired to 00h
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
Description
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
Description
This register sets the value for the Master Latency Timer which
starts counting when the master asserts FRAME#.
Reset to 0
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A