PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 67

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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11
11.1
11.2
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the
last master that used the PCI bus. That is, PI7C7300A keeps the secondary bus grant
asserted to a particular master until a new secondary bus request comes along. After
reset, PI7C7300A parks the secondary bus at itself until transactions start occurring on
the secondary bus. If the internal arbiter is disabled, PI7C7300A parks the secondary bus
only when the reconfigured grant signal, S_REQ#[0], is asserted and the secondary bus is
idle.
COMPACT PCI HOT SWAP
Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and
removing PCI boards form a Compact PCI system without powering down the system.
The PI7C7300A is Hot Swap Friendly silicon that supports all the cPCI Hot Swap
Capable features and adds support for Software Connection Control. Being Hot Swap
Friendly, the PI7C7300A supports the following:
When the PI7C7300A resides on the Compact PCI add-in card, the Primary Bus must be
the bus that is inserted into the Compact PCI system. To perform the Hot Swap function,
the device must be configured according to the CPCI Hot-Swap Specifications. For the
PI7C7300A, the only path for configuration is through the Primary Bus. The bridge may
not be configured through either secondary buses. If the user chooses to use the
secondary buses for insertion, an external register needs to be provided for the Hot Swap
Control Status Register.
CLOCKS
This chapter provides information about the clocks.
PRIMARY CLOCK INPUTS
PI7C7300A implements a primary clock input for the PCI interface. The primary
interface is synchronized to the primary clock input, P_CLK, and the secondary interface
is synchronized to the secondary clock. The secondary clock is derived internally from
the primary clock, P_CLK, through an internal PLL. PI7C7300A operates at a maximum
frequency of 66 MHz.
SECONDARY CLOCK OUTPUTS
PI7C7300A has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock
inputs for up to fifteen external secondary bus devices. The S_CLKOUT[15:0] outputs
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Compliance with PCI Specification 2.2
Tolerates V
Asynchronous Reset
Tolerates Precharge Voltage
I/O Buffers Meet Modified V/I Requirements
Limited I/O Pin Leakage at Precharge Voltage
CC
Page 67 OF 109
from Early Power
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A