PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 55

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300A responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
!
!
!
!
Similarly, during upstream posted write transactions, when PI7C7300A responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
!
!
!
!
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
!
!
PI7C7300A asserts P_PERR# two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C7300A sets the parity error detected bit in the status register of the primary
interface.
PI7C7300A captures and forwards the bad parity condition to the secondary bus.
PI7C7300A completes the transaction normally.
PI7C7300A asserts S_PERR# two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C7300A sets the parity error detected bit in the status register of the secondary
interface.
PI7C7300A captures and forwards the bad parity condition to the primary bus.
PI7C7300A completes the transaction normally.
PI7C7300A sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
PI7C7300A asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
-
-
-
-
The SERR# enable bit is set in the command register.
The posted write parity error bit of P_SERR# event disable register is not set.
The parity error response bit is set in the bridge control register of the secondary
interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C7300A has not detected the parity error on the primary (initiator) bus which
the parity error is not forwarded from the primary bus to the secondary bus.
Page 55 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A