PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 79

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.20
14.1.21
14.1.22
14.1.23
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – Offset 30h
15:4
Bit
19:16
31:20
Bit
31:0
Bit
31:0
Bit
15:0
Prefetchable
Prefetchable
Prefetchable
Prefetchable
I/O Base
Memory Base
Address [31:20]
Function
64-bit addressing
Memory Base
Address [31:20]
Function
Memory Base
Address, Upper
32-bits [63:32]
Function
Memory Limit
Address, Upper
32-bits [63:32]
Function
Address, Upper
16-bits [31:16]
R/W
Type
R/O
R/W
Type
R/W
Type
R/W
Type
R/W
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Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh.
Description
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Reset to 0
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A