PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 6

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
6
7
8
9
10
11
12
4.10
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
7.1
7.2
7.3
7.4
8.1
8.2
8.3
9.1
9.2
11.1
11.2
12.1
12.2
ADDRESS DECODING .................................................................................................................... 40
5.2.1
5.2.2
5.3.1
5.3.2
5.4.1
5.4.2
TRANSACTION ORDERING.......................................................................................................... 46
ERROR HANDLING......................................................................................................................... 50
7.2.1
7.2.2
7.2.3
7.2.4
EXCLUSIVE ACCESS...................................................................................................................... 61
8.2.1
8.2.2
PCI BUS ARBITRATION................................................................................................................. 64
9.2.1
9.2.2
9.2.3
9.2.4
COMPACT PCI HOT SWAP ....................................................................................................... 67
CLOCKS ......................................................................................................................................... 67
RESET............................................................................................................................................. 68
CONCURRENT MODE OPERATION ....................................................................................... 40
ADDRESS RANGES ................................................................................................................... 40
I/O ADDRESS DECODING ........................................................................................................ 41
MEMORY ADDRESS DECODING............................................................................................ 43
VGA SUPPORT ........................................................................................................................... 45
TRANSACTIONS GOVERNED BY ORDERING RULES........................................................ 46
GENERAL ORDERING GUIDELINES...................................................................................... 47
ORDERING RULES .................................................................................................................... 48
DATA SYNCHRONIZATION .................................................................................................... 49
ADDRESS PARITY ERRORS .................................................................................................... 50
DATA PARITY ERRORS ........................................................................................................... 51
DATA PARITY ERROR REPORTING SUMMARY ................................................................. 56
SYSTEM ERROR (SERR#) REPORTING.................................................................................. 60
CONCURRENT LOCKS ............................................................................................................. 61
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A..................................................... 61
ENDING EXCLUSIVE ACCESS ................................................................................................ 63
PRIMARY PCI BUS ARBITRATION......................................................................................... 64
SECONDARY PCI BUS ARBITRATION .................................................................................. 64
PRIMARY CLOCK INPUTS....................................................................................................... 67
SECONDARY CLOCK OUTPUTS............................................................................................. 67
PRIMARY INTERFACE RESET ................................................................................................ 68
SECONDARY INTERFACE RESET .......................................................................................... 68
I/O BASE AND LIMIT ADDRESS REGISTER..................................................................... 42
ISA MODE............................................................................................................................ 42
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ................................ 43
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ......................... 44
VGA MODE.......................................................................................................................... 45
VGA SNOOP MODE ............................................................................................................ 46
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ................. 51
READ TRANSACTIONS ....................................................................................................... 51
DELAYED WRITE TRANSACTIONS ................................................................................... 52
POSTED WRITE TRANSACTIONS...................................................................................... 55
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION.............................................. 61
LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................... 63
SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER ............................. 64
PREEMPTION ..................................................................................................................... 66
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.............................. 66
BUS PARKING..................................................................................................................... 66
Page 6 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A