PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 58

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BIT
Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED
Table 7-5 ASSERTION OF P_PERR#
Table 7-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
!
!
!
X= don’t care
Table 7-5 shows assertion of P_PERR#. This signal is set under the following conditions:
!
!
!
Secondary
Detected Parity
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
P_PERR#
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
The PI7C7300A must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR# signal is detected asserted or a parity error is detected on the
secondary bus.
PI7C7300A is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary
interface.
PI7C7300A detects a data parity error on the primary bus or detects S_PERR#
asserted during the completion phase of a downstream delayed write transaction on
the target (secondary) bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
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Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
3-PORT PCI-TO-PCI BRIDGE
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
ADVANCE INFORMATION
09/25/03 Revision 1.09
Primary /
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
PI7C7300A