PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 42

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.1
5.2.2
and master enable bits, and change them subsequently only when the primary and
secondary PCI buses are idle.
I/O BASE AND LIMIT ADDRESS REGISTER
PI7C7300A implements one set of I/O base and limit address registers in configuration
space that define an I/O address range per port downstream forwarding. PI7C7300A
supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C7300A
to be mapped anywhere in a 4GB I/O address space.
I/O transactions with addresses that fall inside the range defined by the I/O base and limit
registers are forwarded downstream from the primary PCI bus to the secondary PCI bus.
I/O transactions with addresses that fall outside this range are forwarded upstream from
the secondary PCI bus to the primary PCI bus.
The I/O range can be turned off by setting the I/O base address to a value greater than
that of the I/O limit address. When the I/O range is turned off, all I/O trans-actions are
forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range
has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O
range is 4GB in size. The I/O base register consists of an 8-bit field at configuration
address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits
[15:12] of the I/O base address.
The bottom 4 bits read only as 1h to indicate that PI7C7300A supports 32-bit I/O
addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns
the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits
register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits
are read/write. After primary bus reset or chip reset, the value of the I/O base address is
initialized to 0000 0000h.
The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit
field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit
address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is
supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns
the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O
limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit
address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the
I/O limit address is reset to 0000 0FFFh.
Note: The initial states of the I/O base and I/O limit address registers define an I/O range
of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these
registers with their appropriate values before setting either the I/O enable bit or the
master enable bit in the command register in configuration space.
ISA MODE
PI7C7300A supports ISA mode by providing an ISA enable bit in the bridge control
register in configuration space. ISA mode modifies the response of PI7C7300A inside
the I/O address range in order to support mapping of I/O space in the presence of an ISA
bus in the system. This bit only affects the response of PI7C7300A when the transaction
falls inside the address range defined by the I/O base and limit address registers, and only
Page 42 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A