PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 64

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
9.1
9.2
9.2.1
PCI BUS ARBITRATION
PI7C7300A must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to PI7C7300A,
typically on the motherboard. For the secondary PCI bus, PI7C7300A implements an
internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead.
This chapter describes primary and secondary bus arbitration.
PRIMARY PCI BUS ARBITRATION
PI7C7300A implements a request output pin, P_REQ#, and a grant input pin, P_GNT#,
for primary PCI bus arbitration. PI7C7300A asserts P_REQ# when forwarding
transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at
least one pending transaction resides in the queues in the upstream direction, either
posted write data or delayed transaction requests, PI7C7300A keeps P_REQ# asserted.
However, if a target retry, target disconnect, or a target abort is received in response to a
transaction initiated by PI7C7300A on the primary PCI bus, PI7C7300A de-asserts
P_REQ# for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request
has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter
after PI7C7300A has asserted P_REQ#, PI7C7300A initiates a transaction on the
primary bus during the next PCI clock cycle. When P_GNT# is asserted to PI7C7300A
when P_REQ# is not asserted, PI7C7300A parks P_AD, P_CBE, and P_PAR by driving
them to valid logic levels. When the primary bus is parked at PI7C7300A and
PI7C7300A has a transaction to initiate on the primary bus, PI7C7300A starts the
transaction if P_GNT# was asserted during the previous cycle.
SECONDARY PCI BUS ARBITRATION
PI7C7300A implements an internal secondary PCI bus arbiter. This arbiter supports eight
external masters on secondary 1 and seven external masters on secondary 2 in addition to
PI7C7300A. The internal arbiter can be disabled, and an external arbiter can be used
instead for secondary bus arbitration.
SECONDARY BUSARBITRATION USING THE INTERNAL
ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be tied
LOW. PI7C7300A has eight/seven secondary bus 1/2 request input pins, S1_REQ#[7:0],
S2_REQ#[6:0], and has eight/seven secondary bus 1/2 output grant pins, S1_GNT#[7:0],
S2_GNT#[6:0], to support external secondary bus masters. The secondary bus request
and grant signals are connected internally to the arbiter and are not brought out to
external pins when S_CFN# is HIGH.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with
each set taking care of 8 requests/ grants. Each set of masters can be assigned to a high
Page 64 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A