PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 83

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.28
14.1.29
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch
Bit
23:16
24
25
26
31:27
Bit
16
17
31:18
Bit
27:0
Arbiter Control
Reserved
Priority of
Arbiter Park
Reserved
Reserved
Function
Secondary
Interface
Function
Function
Upstream (S1 or
S2 to P) Memory
Base and Limit
Enable
Upstream (S1 or
S2 to P) Memory
Prefetchable
Enable
Function
Hot Swap Time
Slot
Type
R/W
R/O
R/W
R/W
R/O
Type
R/W
R/W
R/O
Type
R/W
Page 83 OF 109
Description
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [23:16] correspond to request inputs S1_REQ[7:0] or
S2_REQ[6:0]
0: low priority
1: high priority
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls whether the S1 or S2 interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
Controls the arbiter’s park function.
0: park to last master
1: park to bridge port S1 or S2
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and Limit
(See offset 50
Reset to 0
0: Upstream memory is prefetchable at Primary
1: Upstream memory is not prefetchable at Primary
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
Hot Swap time slot (15K PCI clocks)
Reset to 0003A98h
th
and 54
th
for upstream memory range)
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A