PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 60

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
X = don’t care
2
3
SYSTEM ERROR (SERR#) REPORTING
PI7C7300A uses the P_SERR# signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section
7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the
following conditions apply:
!
!
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300A
asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and
the SERR# forward enable bit is set in the bridge control register. In addition,
PI7C7300A also sets the received system error bit in the secondary status register.
PI7C7300A also conditionally asserts P_SERR# for any of the following reasons:
!
!
!
!
!
!
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
2
3
(asserted)
For PI7C7300A to assert P_SERR# for any reason, the SERR# enable bit must be
set in the command register.
Whenever PI7C7300A asserts P_SERR#, PI7C7300A must also set the signaled
system error bit in the status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
received)
Delayed read data cannot be transferred from target after 2
target retries received)
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
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(default) attempts to deliver (2
(default) attempts to deliver (2
3-PORT PCI-TO-PCI BRIDGE
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
ADVANCE INFORMATION
24
09/25/03 Revision 1.09
(default) attempts (2
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target retries
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / x
target retries
PI7C7300A
24