PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 65

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
priority group and a low priority group. The low priority group as a whole represents one
entry in the high priority group; that is, if the high priority group consists of n masters,
then in at least every n+1 transactions the highest priority is assigned to the low priority
group. Priority rotates evenly among the low priority group. Therefore, members of the
high priority group can be serviced n transactions out of n+1, while one member of the
low priority group is serviced once every n+1 transactions. Error! Reference source not
found. shows an example of an internal arbiter where four masters, including
PI7C7300A, are in the high priority group, and five masters are in the low priority group.
Using this example, if all requests are always asserted, the highest priority rotates among
the masters in the following fashion (high priority members are given in italics, low
priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1,
m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on.
Figure 9-1 SECONDARY ARBITER EXAMPLE
Each bus master, including PI7C7300A, can be configured to be in either the low priority
group or the high priority group by setting the corresponding priority bit in the arbiter-
control register. The arbiter-control register is located at offset 40h. Each master has a
corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If
the bit is set to 0, the master is assigned to the low priority group. If all the masters are
assigned to one group, the algorithm defaults to a straight rotating priority among all the
masters. After reset, all external masters are assigned to the low priority group, and
PI7C7300A is assigned to the high priority group. PI7C7300A receives highest priority
on the target bus every other transaction, and priority rotates evenly among the other
masters.
Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the
start of each new transaction on the secondary PCI bus. From this point until the time
that the next transaction starts, the arbiter asserts the grant signal corresponding to the
highest priority request that is asserted. If a grant for a particular request is asserted, and
a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant
signal and asserts the grant corresponding to the new higher priority request on the next
PCI clock cycle. When priorities are re-evaluated, the highest priority is assigned to the
next highest priority master relative to the master that initiated the previous transaction.
The master that initiated the last transaction now has the lowest priority in its group.
If PI7C7300A detects that an initiator has failed to assert S1_FRAME# or S2_FRAME#
after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-
asserts the grant. That master does not receive any more grants until it deasserts its
request for at least one PCI clock cycle.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it deasserts another. It de-asserts one grant
Page 65 OF 109
09/25/03 Revision 1.09