PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 43

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
5.3.1
when this address also falls inside the first 64KB of I/O space (address bits [31:16] are
0000h). When the ISA enable bit is set, PI7C7300A does not forward downstream any
I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those
transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base
and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O
address boundary are forwarded as defined by the address range defined by the I/O base
and limit registers.
Accordingly, if the ISA enable bit is set, PI7C7300A forwards upstream those I/O
transactions addressing the top 768 bytes of each aligned 1KB block within the first
64KB of I/O space. The master enable bit in the command configuration register must
also be set to enable upstream forwarding. All other I/O transactions initiated on the
secondary bus are forwarded upstream only if they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C7300A can have I/O space
mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or
anywhere in I/O space above the 64KB boundary.
MEMORY ADDRESS DECODING
PI7C7300A has three mechanisms for defining memory address ranges for forwarding of
memory transactions:
!
!
!
This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To
enable downstream forwarding of memory transactions, the memory enable bit must be
set in the command register in configuration space. To enable upstream forwarding of
memory transactions, the master-enable bit must be set in the command register. The
master-enable bit also allows upstream forwarding of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that memory
transactions are ongoing on the secondary bus, response to the secondary bus memory
transactions is not predictable. Configure the memory-mapped I/O base and limit
address registers, prefetchable memory base and limit address registers, and VGA
mode bit before setting the memory enable and master enable bits, and change them
subsequently only when the primary and secondary PCI buses are idle.
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS
REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses
that cannot automatically be pre-fetched but that can be conditionally prefetched based
on command type should be mapped into this space. Read trans-actions to non-
prefetchable space may exhibit side effects; this space may have non-memory-like
behavior. PI7C7300A prefetches in this space only if the memory read line or memory
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
Page 43 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A