PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 50

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7
7.1
!
PI7C7300A does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
ERROR HANDLING
PI7C7300A checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C7300A always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C100
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C7300A implements the following:
!
!
!
This chapter provides detailed information about how PI7C7300A handles errors. It also
describes error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C7300A checks address parity for all transactions on both buses, for all address and
all bus commands. When PI7C7300A detects an address parity error on the primary
interface, the following events occur:
!
!
!
When PI7C7300A detects an address parity error on the secondary interface, the
following events occur:
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
PERR# and SERR# signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR# event disable register
If the parity error response bit is set in the command register, PI7C7300A does not
claim the transaction with P_DEVSEL#; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C7300A proceeds
normally and accepts the transaction if it is directed to or across PI7C7300A.
PI7C7300A sets the detected parity error bit in the status register.
PI7C7300A asserts P_SERR# and sets signaled system error bit in the status register,
if both the following conditions are met:
-
-
The SERR# enable bit is set in the command register.
The parity error response bit is set in the command register.
Page 50 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A