PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 25

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
When a write transaction is first detected on the initiator bus, and PI7C7300A forwards it
as a delayed transaction, PI7C7300A claims the access by asserting DEVSEL# and
returns a target retry to the initiator. During the address phase, PI7C7300A samples the
bus command, address, and address parity one cycle later. After IRDY# is asserted,
PI7C7300A also samples the first data DWORD, byte enable bits, and data parity. This
information is placed into the delayed transaction queue. The transaction is queued only
if no other existing delayed transactions have the same address and command, and if the
delayed transaction queue is not full. When the delayed write transaction moves to the
head of the delayed transaction queue and all ordering constraints with posted data are
satisfied. The PI7C7300A initiates the transaction on the target bus. PI7C7300A
transfers the write data to the target. If PI7C7300A receives a target retry
in response to the write transaction on the target bus, it continues to repeat the write
transaction until the data transfer is completed, or until an error condition is encountered.
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32
If PI7C7300A is unable to deliver write data after 2
(default) or 2
(maximum)
attempts, PI7C7300A will report a system error. PI7C7300A also asserts P_SERR# if the
primary SERR# enable bit is set in the command register. See Section 7.4 for information
on the assertion of P_SERR#. When the initiator repeats the same write transaction (same
command, address, byte enable bits, and data), and the completed delayed transaction is
at the head of the queue, the PI7C7300A claims the access by asserting DEVSEL# and
returns TRDY# to the initiator, to indicate that the write data
was transferred. If the initiator requests multiple DWORD, PI7C7300A also asserts
STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those
bytes of write data with valid byte enable bits are compared. If any of the byte enable bits
are turned off (driven HIGH), the corresponding byte of write data is not compared.
If the initiator repeats the write transaction before the data has been transferred to the
target, PI7C7300A returns a target retry to the initiator. PI7C7300A continues to return a
target retry to the initiator until write data is delivered to the target, or until an error
condition is encountered. When the write transaction is repeated, PI7C7300A does not
make a new entry into the delayed transaction queue. Section 4.9.3.1 provides detailed
information about how PI7C7300A responds to target termination during delayed write
transactions.
PI7C7300A implements a discard timer that starts counting when the delayed write
completion is at the head of the delayed transaction completion queue. The initial value
of this timer can be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard timer
expires, PI7C7300A discards the delayed write completion from the delayed transaction
completion queue. PI7C7300A also conditionally asserts P_SERR# (see Section 7.4).
4.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C7300A imposes internal address boundaries when accepting write data. The aligned
address boundaries are used to prevent PI7C7300A from continuing a transaction over a
device address boundary and to provide an upper limit on maximum latency. PI7C7300A
returns a target disconnect to the initiator when it reaches the aligned address boundaries
under conditions shown in Table 4–3.
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09/25/03 Revision 1.09