PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 88

no-image

PI7C7300ANAE

Manufacturer Part Number
PI7C7300ANAE
Description
IC PCI-PCI BRIDGE 3PORT 272-BGA
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI7C7300ANAE

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
272-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C7300ANAE
Manufacturer:
Pericom
Quantity:
10 000
14.1.38
14.1.39
14.1.40
14.1.41
MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h
RETRY COUNTER REGISTER – OFFSET 78h
SAMPLING TIMER REGISTER – OFFSET 7Ch
SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER –
OFFSET 80h
Bit
11
15:12
Bit
31:16
Bit
31:0
Bit
31:0
Bit
31:0
Reserved
Master Timeout
Function
Enable Primary
To Hold Request
Longer
Function
Function
Retry Counter
Function
Sampling Timer
Function
Successful I/O
Read Counts on
S1 or S2
Type
R/W
R/O
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Page 88 OF 109
Description
Control’s PI7C7300A’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
Description
Holds the maximum number of PCI clocks that PI7C7300A will wait
for initiator to retry the same cycle before reporting timeout. Master
timeout occurs after 2
Default is 8000h.
Description
Holds the maximum number of attempts that PI7C7300A will try
before reporting retry timeout. Retry count set at 2
Default is 0100 0000h.
Description
Sets the duration (in PCI clocks) during which PI7C7300A will
record the number of successful transactions for performance
evaluation. The recording will start right after this register is
programmed and will be cleared after the timer expires. Maximum
period is 128 seconds at 33MHz.
Reset to 0.
Description
Stores the successful I/O read count on S1 or S2 and is updated when
the sampling timer is active.
Reset to 0
15
PCI clocks.
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
24
PCI clocks.
PI7C7300A

Related parts for PI7C7300ANAE