PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 38

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.3.3
4.9.4
4.9.4.1
Table 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C7300A initiates a delayed read transaction, the abnormal target responses can
be passed back to the initiator. Other target responses depend on how much data the
initiator requests. Table 4-9 shows the response to each type of target termination that
occurs during a delayed read transaction.
PI7C7300A repeats a delayed read transaction until one of the following conditions is
met:
!
!
!
!
After PI7C7300A makes 2
the target bus, PI7C7300A asserts P_SERR# if the primary SERR# enable bit is set (bit 8
of command register for secondary bus S1 or S2) and the delayed-write-non-delivery bit
is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register
(offset 64h). PI7C7300A will report system error. See Section 7.4 for a description of
system error conditions.
TARGET TERMINATION INITIATED BY PI7C7300A
PI7C7300A can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
TARGET RETRY
PI7C7300A returns a target retry to the initiator when it cannot accept write data or
return read data as a result of internal conditions. PI7C7300A returns a target retry to an
initiator when any of the following conditions is met:
For delayed write transactions:
!
!
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C7300A completes at least one data transfer.
PI7C7300A receives a master abort.
PI7C7300A receives a target abort.
PI7C7300A makes 2
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Response
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
24
24
(default) read attempts resulting in a response of target retry.
Page 38 OF 109
(default) attempts of the same delayed read transaction on
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A