TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 98

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

4. DMA Interface > Operating Modes
4.4.1
98
Figure 19: Linked-list Mode
Linked-List Descriptors
The PCI/X Master is responsible for fetching descriptors from local memory when using
Linked-List Mode. Each descriptor consumes 40 bytes and must be aligned on 64-bit
boundaries. This structure helps minimize the PCI/X bus bandwidth used when fetching
descriptors.
Table 4
Table 4: DMA Controller Linked-List Descriptors
Each field within the descriptor corresponds to a DMA control register. When a descriptor is
loaded by the DMA controller, each field is placed into its corresponding DMA control
register (see
The descriptors are linked together by the DNLA register (that is, the DNLA field within a
descriptor). This field contains the address within PCI address space where the next descriptor
may be found. The Last Link-descriptor Address field (LLA) within the DNLA indicates that
this is the last descriptor.
Descriptors are not prefetched by the PCI/X Master. A linked-list mode command is started
by the PCI/X Master reading one descriptor. The DMA controller then performs the transfer
associated with that descriptor. If there are more descriptors to be executed, the fetching of the
next descriptor does not occur until the current transfer has completed.
Table
Build
Desc
Offset
0x00
0x08
0x10
0x18
0x20
Processor
shows the format of a descriptor.
Program
Section 10.4.76 on page
(Start)
DGO
63
Linked List
Fetch
Desc
DNLAU
DDAU
DSAU
DCNT
DSAT
Transfer
Linked-List Mode, Various Transfers
Read
Write
Data
Data
327).
Fetch
Desc
32
Bits
31
Transfer
Read
Data
Tsi148 PCI/X-to-VME Bus Bridge User Manual
Write
Data
DNLAL
DDAL
DDAT
DDBS
DSAL
Fetch
Desc
Transfer
Pattern
Write
0
80A3020_MA001_13
Done