TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 261

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TSI148-133CL

Manufacturer Part Number
TSI148-133CL
Description
IC PCI-VME BRIDGE 456PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
Tsi148&Trade;r
Datasheets

Specifications of TSI148-133CL

Applications
PCI-to-VME Bridge
Interface
PCI
Voltage - Supply
3.3V
Package / Case
456-PBGA
Mounting Type
Surface Mount
Package Type
BGA
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1906

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TSI148-133CL
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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Manufacturer:
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Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
REQ64S (REQ64 Status): When this bit is set, the REQ64_ signal was sampled high at the
rising edge of LRSTI_ and the PCI/X A/D bus is configured for 32-bit. When this bit is clear,
the REQ64_ signal was sampled low at the rising edge of reset and the PCI/X A/D bus is
configured for 64-bit operation.
M66ENS (66 MHz Enable Status): When this bit is set, the M66EN signal was sampled
high at the rising edge of LRSTI_. When this bit is clear, the M66EN signal was sampled low
at the rising edge of LRSTI_.
FRAMES (FRAME Status): When this bit is set, the FRAME_ signal was sampled high at
the rising edge of LRSTI_. When this bit is clear, the FRAME_ signal was sampled low at the
rising edge of LRSTI_.
IRDYS (IRDY Status): When this bit is set, the IRDY_ signal was sampled high at the rising
edge of LRSTI_. When this bit is clear, the IRDY_ signal was sampled low at the rising edge
of LRSTI_.
DEVSELS (DEVSEL Status): When this bit is set, the DEVSEL_ signal was sampled high
at the rising edge of LRSTI_. When this bit is clear, the DEVSEL_ signal was sampled low at
the rising edge of LRSTI_.
STOPS (STOP Status): When this bit is set, the STOP_ signal was sampled high at the rising
edge of LRSTI_. When this bit is clear, the STOP_ signal was sampled low at the rising edge
of LRSTI_.
TRDYS (TRDY Status): When this bit is set, the TRDY_ signal was sampled high at the
rising edge of LRSTI_. When this bit is clear, the TRDY_ signal was sampled low at the
rising edge of LRSTI_.
10. Registers > Register Map
261

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