TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 249

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

VME Master Control Register
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
10:8
Bits
7:5
4:3
1:0
2
Reserved
VREQL
VSA (VMEbus Stop Acknowledge): When this bit is set, the VME Master has obtained
mastership of the VMEbus in response to the VS request. This bit is not set if the VME
Master has obtained VMEbus ownership for any other reason.
VS (VMEbus Stop): When this bit is set, the Tsi148 requests the VMEbus. When VMEbus
ownership has been obtained, the VSA bit is set. VMEbus ownership is maintained until the
VS bit is cleared. While the VS bit is set, the PCI/X to VMEbus channel and DMA controllers
are prevented for accessing the VMEbus. This bit is used to ensure that the VMEbus is idle
before the LRESET bit is set. This bit is cleared and the VMEbus released when the LRSTI_
signal is received.
DHB (Device Has Bus): When this bit is set, the VME Master has obtained mastership of the
VMEbus in response to the DWB request. This bit is not set if the VME Master has obtained
VMEbus ownership for any other reason.
DWB (Device Wants Bus): When this bit is set, the VME Master requests the VMEbus.
When VMEbus ownership has been obtained, the DHB bit is set. VMEbus ownership is
maintained until the DWB bit is cleared. While the DWB bit is set, the PCI/X to VMEbus
channel and DMA controllers may access the VMEbus.
RMWEN (RMW Enable): If set, the VME Master RMW function is enabled. If cleared, the
VME Master RMW function is disabled.
A64DS (A64 Data Strobes): If set, the VME Master asserts both the DS0_ and DS1_ signals
during an A64 address phase. If cleared, the VME Master asserts the data strobes based on the
following data phase.
VFAIR
VTON
VREL
Name
VME Master Time On
N/A
VME Master Release Mode
VME Master Fair Mode
VME Master Request Level
Function
PCFS
Space
Type
R/W
R/W
R/W
R/W
R
10. Registers > Register Map
Reset
P/S/L
P/S/L
P/S/L
P/S/L
N/A
By
Reset
Value
0x00
0x00
0x00
0x00
11b
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