TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 92

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3. PCI/X Interface > PCI-X Mode
3.3.2
3.3.2.1
3.3.2.2
92
PCI-X Master
The PCI-X Master can generate the following PCI-X bus commands:
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PCI-X Master Buffers
The PCI-X Master has one read buffer and one write buffer. The buffers are segmented into
two parts: a data queue and a command queue. Both the read and write buffer command
queues are six entries deep. The read and write data buffers are 4 Kbyte.
The read buffer stores Linkage Module commands when servicing a read request from the
VMEbus to the PCI-X bus. The PCI-X Master requests the PCI-X bus when it receives a read
command from the Linkage Module. After the read transaction has been satisfied on the
PCI-X bus, and the read buffer data queue has the requested data, the PCI-X Master transfers
the data through the Linkage Module to the VMEbus.
The write buffer stores Linkage Module commands and data. The PCI-X Master requests the
PCI-X bus when it receives a command and write data from the Linkage Module. The write
buffer is considered full when either the command or data queue is full.
PCI-X Master Bandwidth Control
The PCI-X bus latency timer can be used to control the PCI-X bus bandwidth used by Tsi148.
The PCI-X Master requests the PCI-X bus when it has a transaction to complete (for example,
when the PCI-X Master receives a command from the Linkage Module or when it needs to
complete a previously received command). The PCI-X Master maintains mastership of the
PCI-X bus until the linkage command is completed or until the PCI-X bus grant is removed
and the latency timer has expired.
Split completion
Dual address cycle (A dual address cycle is generated when the PCI address is greater
than 32 bits)
Memory read block
Memory write block
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13