TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 119

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

5.2.1
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Reset Inputs and Outputs
Tsi148 has the following reset inputs and reset outputs:
•
Reset Inputs
— Power-up Reset (PURSTI_): This signal resets all of the Tsi148 logic. When it is
— VMEbus System Reset In (SRSTI_): This signal resets all of the Tsi148 logic which
— PLL Reset (PLL_RSTI_): This signal resets the Tsi148 PLL. The PLL_RSTI_ pin
— JTAG Test Reset (TRST_): Provides asynchronous initialization of the TAP
— Local Bus (PCI/X) Reset In (LRSTI_): Assertion of this signal resets all Tsi148’s
— Local System Reset (LSRSTI_): This signal is used to reset the VMEbus from the
asserted both the PCI/X and VMEbus can be reset through the Tsi148 reset outputs
LRSTO_ and SRSTO.
is sensitive to SYSRESET. Typically, the backplane SYSRESET_ is connected to
this signal through a transceiver. When SRSTI_ is asserted the PCI/X bus can be
reset through the Tsi148 reset output LRSTO_.
has to be asserted until the clock and power are stable.
controller in the Tsi148. This signal must be tied to ground if JTAG is not used in the
system. If JTAG is used in the system, the TRST_ input must be asserted low at the
negation of the PURST_ input and then held high during boundary scan testing.
internal logic except the logic required for VME services and clock service (see
Figure
PCI/X bus. When this signal is asserted the Tsi148 output SRSTO is asserted. This
signal allows on board logic to generate a VMEbus system reset.
30). This signal should be connected to the board’s local bus (PCI/X) reset.
5. Resets, Clocks, and Power-up Options > Resets
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