TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 165

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

Table 16: Miscellaneous Signal Descriptions
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Signal Group
Configuration
Hardware
Interrupt
Control
Reset
PLL
LRSTI_
Local Reset
Input
LRSTO_
Local Reset
Output
LSRSTI_
Local System
Reset
Input
PURSTI_
Power Up
Reset
Input
INTA_-
INTD_
HWC_PFU
PCIPUEN
PCIMC
PLL_TEN
PLL_TUNE
[9:0]
PLL_RSTI_
PLL_OUTA
Signal Name
Active
High
High
High
High
High
Low
Low
Low
Low
Low
Low
-
I/O
O
O
I
I
I
I
I
I
I
I
I
-
When this signal is asserted, the PCI bus internal logic is reset. This
signal should be connected to the boards local bus reset signal.
When this signal is asserted, the PCI bus logic on the board should be
reset. This signal should be combined with other reset signals to generate
the local bus reset signal.
When this signal is asserted, the LRSTO signal is asserted. This signal
allows on board logic to generate a VMEbus system reset.
PURSTI_ is asserted at power up.
These pins are the PCI bus interrupt outputs.
When Tsi148 is configured in 32-bit PCI mode and this signal is low, the
64-bit extension signals are driven. When Tsi148 is configured in 32-bit
PCI mode and this signal is high, the 64-bit extension signals are
tri-stated.
When this signal is asserted, the internal PCI bus pull ups are enable.
When this signal is negated, the internal PCI bus pull ups are disabled.
When this signal is asserted, the PCI drivers are configured with a 40
ohm impedance for point-to-point operation. When this signal is negated,
the PCI drivers are configured with a 20 ohm impedance for multi-point
operation.
When this signal is high, the PLL_TUNE signals are used to tune the
PLL.
When the PLL_TEN signal is asserted, these signals are used to tune the
PLL. When PLL_TEN signal is negated, the PLL tune bits are internally
controlled.
When this signal is asserted, the PLL is reset.
PLL Output: This output is internally disabled.
8. Signals and Pins > Detailed Signal Descriptions
Description
165