TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 72

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

3. PCI/X Interface > PCI Mode
72
When a PCI bus memory read line burst transfer is received, the read command passed to the
Linkage Module requests 32 bytes. When a PCI bus memory read multiple command is
received, the data size depends on the PFS bits. The read sizes are 64, 128, 256, or 512 bytes.
The PCI read operations are summarized in
Table 3: PCI Read Data Size
The PCI bus master is retried until all the requested data is available in the PCI Target read
buffer. The read then completes on the PCI bus.
Single Beat
Transfer
Burst
Burst
Burst
Burst
Burst
Burst
Burst
PCI
Care must be used when setting the value in the PFS field because the VMEbus
read is completed before data is transferred on the PCI bus. If the value is too
large, time is wasted reading data that is not used. If the value is too small,
additional PCI bus commands are required. The optimum setting depends on the
PCI bus masters and the requirements of the application. In many cases, the only
read transfers from the PCI bus to the VMEbus are single beat processor load
operations and prefetching is not required.
Read Multiple
Read Multiple
Read Multiple
Read Multiple
Command
Read Line
Read
Read
PCI
X
MRPFD
Table
Bit
X
X
X
X
X
X
1
0
3.
Tsi148 PCI/X-to-VME Bus Bridge User Manual
PFS
Bits
X
X
X
X
0
1
2
3
80A3020_MA001_13
Single Beat
Single Beat
Command
128 bytes
256 bytes
512 bytes
Linkage
32 bytes
32 bytes
64 bytes