STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 96

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

Serial interfaces
9.9.2
Table 57.
96/220
31
15
30
14
SPI configuration register (SCx_SPICFG)
Address offset: 0xC858 (SC1_SPICFG) and 0xC058 (SC2_SPICFG)
Reset value:
SPI configuration register (SCx_SPICFG)
Bit 5 SC_SPIRXDRV: Receiver-driven mode selection bit (SPI master mode only). Clear this bit to
Bit 4 SC_SPIMST: Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave
Bit 3 SC_SPIRPT: This bit controls behavior on a transmit buffer underrun condition in slave mode.
Bit 2 SC_SPIORD: This bit specifies the bit order in which SPI data is transmitted and received.
Bit 1 SC_SPIPHA: Clock phase configuration: clear this bit to sample on the leading (first edge) and
Bit 0 SC_SPIPOL: Clock polarity configuration: clear this bit for a rising leading edge and set this bit
29
13
initiate transactions when transmit data is available. Set this bit to initiate transactions when the
receive buffer (FIFO or DMA) has space.
mode.
Clear this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to
this bit take effect when the transmit FIFO is empty and the transmit serializer is idle.
0: Most significant bit first.
set this bit to sample on the second edge.
for a falling leading edge.
28
12
27
11
Reserved
0x0000 0000
STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
26
10
25
9
Doc ID 16252 Rev 9
24
8
Reserved
23
7
22
6
1: Least significant bit first.
SC_SPI
RXDRV
21
rw
5
SC_S
PIMS
20
rw
T
4
SC_SP
IRPT
19
rw
3
SC_SP
IORD
18
rw
2
SC_SP
IPHA
17
rw
1
SC_SP
IPOL
16
rw
0