STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 30

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

Embedded memory
4.2.1
4.2.2
4.3
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Direct memory access (DMA) to RAM
Several of the peripherals are equipped with DMA controllers allowing them to transfer data
into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general
purpose ADC, and both serial controllers. In the case of the serial controllers, the DMA is full
duplex so that a read and a write to RAM may be requested at the same time. Thus there
are six DMA channels in total.
The STM32W108 integrates a DMA arbiter that ensures fair access to the microprocessor
as well as the peripherals through a fixed priority scheme appropriate to the memory
bandwidth requirements of each master. The priority scheme is as follows, with the top
peripheral being the highest priority:
1.
2.
3.
4.
5.
6.
RAM memory protection
The STM32W108 integrates two memory protection mechanisms. The first memory
protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU)
described in the Memory Protection Unit section. The MPU may be used to protect any area
of memory. MPU configuration is normally handled by software. The second memory
protection mechanism is through a fine granularity RAM protection module. This allows
segmentation of the RAM into blocks where any block can be marked as write protected. An
attempt to write to a protected RAM block using a user mode write results in a bus error
being signaled on the AHB System bus. A system mode write is allowed at any time and
reads are allowed in either mode. The main purpose of this fine granularity RAM protection
module is to notify the stack of erroneous writes to system areas of memory. RAM protection
is configured using a group of registers that provide a bit map. Each bit in the map
represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for
STM32W108CC and STM32W108CZ. When the bit is set the block is write protected.
The fine granularity RAM memory protection mechanism is also available to the peripheral
DMA controllers. A register bit is provided to enable the memory protection to include DMA
writes to protected memory. If a DMA write is made to a protected location in RAM, a
management interrupt is generated. At the same time the faulting address and the
identification of the peripheral is captured for later debugging. Note that only peripherals
capable of writing data to RAM, such as received packet data or a received serial port
character, can generate this interrupt.
Memory protection unit
The STM32W108 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The
MPU controls access rights and characteristics of up to eight address regions, each of
which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical
Reference Manual (DDI 0337A) for a detailed description of the MPU.
ST software configures the MPU in a standard configuration and application software should
not modify it. The configuration is designed for optimal detection of illegal instruction or data
General Purpose ADC
Serial Controller 2 Receive
Serial Controller 2 Transmit
MAC
Serial Controller 1 Receive
Serial Controller 1 Transmit
STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
Doc ID 16252 Rev 9