STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 142

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

General-purpose timers
142/220
Figure 48. Triggering timer 2 with update of Timer 1
As in the previous example, both counters can be initialized before starting counting.
Figure 47
mode instead of gated mode (TIM_SMS = 110 in the TIM2_SMCR register).
Figure 49. Triggering Timer 2 with enable of Timer 1
Starting both timers synchronously in response to an external trigger
This example, sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2
with the enable of Timer 1. Refer to
aligned, Timer 1 must be configured in master/slave mode (slave with respect to TI1, master
with respect to Timer 2):
●
●
●
Configure Timer 1 in master mode to send its Enable as trigger output (TIM_MMS =
001 in the TIM1_CR2 register).
Configure Timer 1 slave mode to get the input trigger from TI1 (TIM_TS = 100 in the
TIM1_SMCR register).
Configure Timer 1 in trigger mode (TIM_SMS = 110 in the TIM1_SMCR register).
shows the behavior with the same configuration shown in
STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
Doc ID 16252 Rev 9
Figure 45
for connections. To ensure the counters are
Figure
48, but in trigger