STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 167

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter
Table 109. Typical ADC input configurations (continued)
Input range
ADC inputs can be routed through input buffers to expand the input voltage range. The input
buffers have a fixed 0.25 gain and the converted data is scaled by that factor.
With the input buffers disabled the single-ended input range is 0 to VREF and the differential
input range is -VREF to +VREF. With the input buffers enabled the single-ended range is 0
to VDD_PADS and the differential range is -VDD_PADS to +VDD_PADS.
The input buffers are enabled for the ADC P and N inputs by setting the ADC_HVSELP and
ADC_HVSELN bits respectively, in the ADC_CFG register. The ADC accuracy is reduced
when the input buffer is selected.
Sample time
ADC sample time is programmed by selecting the sampling clock and the clocks per
sample.
●
●
Table 110
results.
Table 110. ADC sample times
ADC5
GND
VREF
VDD_PADSA/2
ADC_PERIOD
ADC P input
The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the
ADC_CFG register is clear, the 6 MHz clock is used; if it is set, the 1 MHz clock is
selected. The 6 MHz sample clock offers faster conversion times but the ADC
resolution is lower than that achieved with the 1 MHz clock.
The number of clocks per sample is determined by the ADC_PERIOD bits in the
ADC_CFG register. ADC_PERIOD values select from 32 to 4096 sampling clocks in
powers of two. Longer sample times produce more significant bits. Regardless of the
sample time, converted samples are always 16-bits in size with the significant bits left-
aligned within the value.
0
1
2
3
4
5
shows the options for ADC sample times and the significant bits in the conversion
Sample
clocks
1024
128
256
512
32
64
VREF/2
ADC4
VREF/2
VREF/2
ADC N input
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock
1024
128
256
512
Sample time (µs)
32
64
Doc ID 16252 Rev 9
5.33
10.7
21.3
42.7
85.3
ADC_MUXP
170
10
11
5
8
Sample frequency (kHz)
0.977
31.3
15.6
7.81
3.91
1.95
ADC_MUXN
4
9
9
9
93.8
46.9
23.4
11.7
5.86
188
Calibration
Differential
Calibration
Calibration
Purpose
Significant
bits
10
5
6
7
8
9
167/220