STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet
STM32W108HBU61TR
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STM32W108HBU61TR Summary of contents
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High-performance, IEEE 802.15.4 wireless system-on-chip Features ■ Complete system-on-chip – 32-bit ARM® Cortex™-M3 processor – 2.4 GHz IEEE 802.15.4 transceiver & lower MAC – 128/192/256-Kbyte Flash, 8/12/16-Kbyte RAM memory – AES128 encryption accelerator – Flexible ADC, SPI/UART/I communications, and general-purpose ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.6.3 9.6.4 9.6.5 9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 9.13.11 Receive DMA end address register B (SCx_RXENDB 108 9.13.12 Receive DMA count register A (SCx_RXCNTA ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2 159 10.3.13 Timer x capture/compare 3 register (TIMx_CCR3 ...
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Contents 12.2 Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 14.9.2 14.9.3 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STM32W108 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of 802.15.4-based systems. Figure 1. STM32W108 block diagram ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ received packets. A packet trace interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the STM32W108. The STM32W108 offers a number of advanced power management features that ...
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Description 1.2 Overview 1.2.1 Functional description The STM32W108 radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely, WIFI and Bluetooth), and to minimize power consumption. ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction. The STM32W108 contains three power domains. ...
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Documentation conventions STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 2 Documentation conventions Table 1. Description of abbreviations used for bitfield access Abbreviation Read/Write (rw) Read-only (r) Write only (w) Read/Write in (MPU) Privileged mode only (rws) 1. The conditions under which the ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description 3 Pinout and pin description Figure 2. 48-pin VFQFPN pinout VDD_24MHZ VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA PC5, TX_ACTIVE nRESET ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 3. 40-pin VFQFPN pinout VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA PC5, TX_ACTIVE Table 2. Pin descriptions 48-Pin 40-Pin Package Package Signal Pin no. Pin no ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no BIAS_R 10 9 VDD_PADSA PC5 11 10 TX_ACTIVE 12 11 nRESET PC6 OSC32B 13 nTX_ACTIVE ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB3 TIM2_CH3 (see Pin 22) UART_CTS 19 15 SC1SCLK PB4 TIM2_CH4 (see also Pin 24 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA0 TIM2_CH1 (see also Pin 30 SC2MOSI PA1 TIM2_CH3 (see also Pin 19) SC2SDA 22 ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA2 TIM2_CH4 (see also Pin 20) SC2SCL 24 20 SC2SCLK PA3 SC2nSSEL TRACECLK (see also Pin 25 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA4 ADC4 PTI_EN 26 22 TRACEDATA2 PA5 ADC5 PTI_DATA 27 23 nBOOTMODE TRACEDATA3 28 24 VDD_PADS PA6 ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB1 SC1MISO SC1MOSI 30 25 SC1SDA SC1TXD TIM2_CH1 (see also Pin 21) 22/220 Direction I/O Digital I/O ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB2 SC1MISO SC1MOSI 31 26 SC1SCL SC1RXD TIM2_CH2 (see also Pin 25) SWCLK 32 27 JTCK PC2 ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PC3 34 29 JTDI PC4 JTMS 35 30 SWDIO PB0 VREF VREF 36 IRQA TRACECLK (see also ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PC1 ADC3 SWO (see also Pin 38 31 33) TRACEDATA0 39 32 VDD_MEM PC0 JRST 40 33 ...
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Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB6 ADC1 42 35 IRQB TIM1_CH1 PB5 ADC0 43 TIM2CLK TIM1MSK 44 36 VDD_CORE 45 37 VDD_PRE ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 4 Embedded memory Figure 4. STM32W108xB memory mapping 0xE00FFFFF 0xE00FF000 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x42002XXX 0x42000000 0x40000XXX 0x40000000 0x22002000 0x22000000 0x20001FFF 0x20000000 0x080409FF Customer Info Block (0.5kB) 0x08040800 0x080407FF ...
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Embedded memory Figure 5. STM32W108CC and STM32W108CZ memory mapping 28/220 STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Doc ID 16252 Rev 9 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 4.1 Flash memory The STM32W108 provides Flash memory in four separate blocks as follows: ● Main Flash Block (MFB) ● Fixed Information Block (FIB) ● Fixed Information Block Extension (FIB-EXT) ● Customer Information Block (CIB) ...
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Embedded memory 4.2.1 Direct memory access (DMA) to RAM Several of the peripherals are equipped with DMA controllers allowing them to transfer data into and out of RAM autonomously. This applies to the radio (802.15.4 MAC), general purpose ADC, and ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ accesses illegal access is attempted, the MPU captures information about the access type, the address being accessed, and the location of the offending software. This simplifies software debugging and increases the reliability of ...
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Radio frequency module 5 Radio frequency module The radio module consists of an analog front end and digital baseband as shown in Figure 1: STM32W108 block 5.1 Receive (Rx) path The Rx path uses a low-IF, super-heterodyne receiver that rejects ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 5.2.1 Tx baseband The STM32W108 Tx baseband in the digital domain spreads the 4-bit symbol into its IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to calibrate the Tx module to reduce ...
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Radio frequency module The primary features of the MAC are: ● CRC generation, appending, and checking ● Hardware timers and interrupts to achieve the MAC symbol timing ● Automatic preamble and SFD pre-pending on Tx packets ● Address recognition and ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 6 System modules System modules encompass power, resets, clocks, system timers, power management, and encryption. Figure 6 Figure 6. System module block diagram recomended connections for internal regulator External Regulator optional connections for external regulator ...
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System modules 6.1 Power domains The STM32W108 contains three power domains: ● An "always on domain" containing all logic and analog cells required to manage the STM32W108's power modes, including the GPIO controller and sleep timer. This domain must remain ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 6.2 Resets The STM32W108 resets are generated from a number of sources. Each of these reset sources feeds into central reset detection logic that causes various parts of the system to be reset depending on ...
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System modules Deep sleep reset The Power Management module informs the Reset Generation module of entry into and exit from the deep sleep states. The deep sleep reset is applied in the following states: before entry into deep sleep, while ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ ● PRESETHV ● PRESETLV Table 4 shows which reset sources generate certain resets. Table 4. Generated resets Reset source POR HV POR LV (in deep sleep) POR LV (not in deep sleep) RSTB Watchdog reset ...
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System modules Bit 4 SW_RST: When set to ‘1’, the reset is due to a software reset. Bit 3 W_DOG: When set to ‘1’, the reset is due to watchdog expiration. Bit 2 RSTB_PIN: When set to ‘1’, the reset ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 7 shows a block diagram of the clocks in the STM32W108. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. Figure 7. Clocks ...
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System modules calibrated accuracy of OSCHF is ±250 kHz ±40 ppm. The UART and ADC peripherals may not be usable due to the lower accuracy of the OSCHF frequency. See also Section 14.5.1: High frequency internal clock characteristics on page ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ In addition to these modes, further automatic control is invoked by hardware when flash programming is enabled. To ensure accuracy of the flash controller's timers, the FCLK frequency is forced to 12 MHz during flash ...
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System modules Bit 0 CPU_CLK_SEL: When set to ‘0’, 12-MHz CPU clock is selected. When set to ‘1’, 24-MHz CPU clock is selected. Note that the clock selection also determines if RAM controller is running at the same speed as ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 6.4.3 Event timer The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer ...
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System modules Bits [15:0] WDOG_CTRL: Write 0xDEAD to disable or 0xEABE to enable. Watchdog restart register (WDOG_RESTART) Write any value to this register to kick-start the watchdog. Address: Reset value: Sleep timer configuration register (SLEEPTMR_CFG) This register sets the various ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Sleep timer count high register (SLEEPTMR_CNTH) Table 12 Bits [15:0] SLEEPTMR_CNTH_FIELD: Sleep timer counter high value [31:16]. Reading this register updates the SLEEP_COUNT_L for subsequent ...
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System modules Bits [15:0] SLEEPTMR_CMPAH_FIELD: Sleep timer compare A high value [31:16]. Sleep timer compare value, writing updates COMP_A_H (directly) and COMP_A_L (from hold register). Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bits [15:0] SLEEPTMR_CMPBH_FIELD: Sleep timer compare B high value [31:16]. Sleep timer compare value, writing updates COMP_B_H (directly) and COMP_B_L (from hold register). Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG ...
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System modules Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B Note: Bits are cleared when set to ‘1’. Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A Note: Bits are cleared when set to ‘1’. Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bit 1 SLEEPTMR_CLK10KEN: Enables 10kHz internal RC during deep Note: Bits are cleared when set to ‘1’. Bit 0 SLEEPTMR_CLK32KEN: Enables 32kHz external XTAL Note: Bits are cleared when set to ‘1’. 6.5 Power management ...
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System modules The following source is only available in deep sleep 0 since the SWJ is required to write memory to set this wake source and the SWJ only has access to some registers in deep sleep 0. ● Wake ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 6.5.2 Basic sleep modes The power management state diagram in management controller. Figure 8. Power management state diagram DEEP SLEEP PRE- DEEP SLEEP CSYSPWRUPREQ & INHIBIT Figure 8 shows the basic operation of the power ...
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System modules In normal operation an application may request one of two low power modes through program execution: ● Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the Cortex System Control register (SCS_SCR) is ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ initiates access while the STM32W108 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108 is properly powered and ready. For more information regarding the ...
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Integrated voltage regulator STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 7 Integrated voltage regulator The STM32W108 integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies. The 1V8 regulator supplies the analog and memories, and the 1V25 regulator ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Integrated voltage regulator Table 21. 1.8 V integrated voltage regulator specifications (continued) Parameter 1V8 regulator start-up time 1V25 regulator start-up time An external 1.8 V regulator may replace both internal regulators. The STM32W108 can control ...
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General-purpose input/outputs 8 General-purpose input/outputs The STM32W108 has 24 multi-purpose GPIO pins that may be individually configured as: ● General purpose output ● General purpose open-drain output ● Alternate output controlled by a peripheral device ● Alternate open-drain output controlled ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- 8.1 Functional description 8.1.1 GPIO ports The 24 GPIO pins are grouped into three ports: PA, PB, and PC. Individual GPIOs within a port are numbered according to their bit ...
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General-purpose input/outputs Table 22. GPIO configuration modes (continued) GPIO mode Alternate Output (open- drain) Alternate Output (push- pull) SPI SCLK Mode If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- Table 24. GPIO forced functions GPIO GPIO_EXTREGEN bit set in the PA7 GPIO_DBGCFG register PC0 Debugger interface is active in JTAG mode PC2 Debugger interface is active in JTAG mode PC3 Debugger interface ...
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General-purpose input/outputs 8.1.6 GPIO modes Analog mode Analog mode enables analog functions, and disconnects a pin from the digital input and output logic. Only the following GPIO pins have analog functions: ● PA4, PA5, PB5, PB6, PB7, and PC1 can ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- When configured in output mode: ● The output drivers are enabled and are controlled by the value written to GPIO_PxOUT: ● In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the ...
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General-purpose input/outputs activity caused a wake event, but not which specific GPIO was responsible. Instead, software should read the state of the GPIOs on waking to determine the cause of the event. The register GPIO_WAKEFILT contains bits to enable digital ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- Table 25. IRQC/D GPIO selection (continued) GPIO_IRQxSEL some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for ...
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General-purpose input/outputs Table 26. GPIO signal assignments (continued) GPIO PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 1. Default signal assignment (not remapped). 2. Overrides during reset as an input with pull ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- 8.5 General-purpose input / output (GPIO) registers 8.5.1 Port x configuration register (Low) ( Address offset: 0xB000 (GPIO_PACFGL), 0xB400 (GPIO_PBCFGL) and 0xB800 (GPIO_PCCFGL) Reset value: Table 27. Port x configuration register (Low) ( ...
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General-purpose input/outputs Bits [15:12] Px7_CFG: GPIO configuration control. 0x0: Analog, input or output (GPIO_PxIN always reads 1). 0x1: Output, push-pull (GPIO_PxOUT controls the output). 0x4: Input, floating. 0x5: Output, open-drain (GPIO_PxOUT controls the output). 0x8: Input, pulled up or down ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- 8.5.4 Port x output data register (GPIO_PxOUT) Address offset: 0xB00C (GPIO_PAOUT), 0xB40C (GPIO_PBOUT) Reset value: Table 30. Port x output data register (GPIO_PxOUT ...
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General-purpose input/outputs Bit 2 Px2: Write 1 to clear the output data bit for Px2 (writing 0 has no effect). Bit 1 Px1: Write 1 to clear the output data bit for Px1 (writing 0 has no effect). Bit 0 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- Bit 7 Px7: Write 1 to enable wakeup monitoring of Px7. Bit 6 Px6: Write 1 to enable wakeup monitoring of Px6. Bit 5 Px5: Write 1 to enable wakeup monitoring of Px5. ...
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General-purpose input/outputs Bits [4:0] SEL_GPIO: Pin assigned to IRQx. 0x00: PA0. 0x01: PA1. 0x02: PA2. 0x03: PA3. 0x04: PA4. 0x05: PA5. 0x06: PA6. 0x07: PA7. 0x08: PB0. 0x09: PB1. 0x0A: PB2. 0x0B: PB3. 0x0C: PB4. 8.5.10 GPIO interrupt x configuration ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ General-purpose input/out- 8.5.11 GPIO interrupt flag register (INT_GPIOFLAG) Address offset: 0xA814 Reset value: Table 37. GPIO interrupt flag register (INT_GPIOFLAG Bit 3 INT_IRQDFLAG: IRQD interrupt ...
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General-purpose input/outputs 8.5.13 GPIO debug status register (GPIO_DBGSTAT) Address offset: 0xBC04 Reset value: Table 39. GPIO debug status register (GPIO_DBGSTAT Bit 3 GPIO_BOOTMODE: The state of the nBOOTMODE signal sampled ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9 Serial interfaces 9.1 Functional description The STM32W108 has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications. ● SPI (Serial Peripheral Interface), master or slave 2 ...
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Serial interfaces Figure 10. Serial controller block diagram SCx Interrupt SCx_MODE SCx TX DMA channel SCx RX DMA channel 9.2 Configuration Before using a serial controller, it should be configured and initialized as follows: 1. Set up the parameters specific ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 40. SC1 GPIO usage and configuration Interface SC1MOSI alternate SPI - Master output (push-pull) SC1MISO alternate SPI - Slave output (push-pull) SC1SDA alternate Master output (open-drain) TXD alternate UART output ...
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Serial interfaces Table 42. SPI master GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.3.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following register settings: ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 43. SPI master mode formats (continued) SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL Same as above except data is sent LSB first ...
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Serial interfaces Every time an automatic character transmission starts, a transmit underrun is detected as there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register is set. After automatic character transmission is disabled, no more ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 44. SPI slave GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.4.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI slave mode. SPI slave mode is enabled by the ...
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Serial interfaces Table 45. SPI slave mode formats (continued) SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL nSSEL SCLK MOSI in MISO out Same as above except LSB first instead of MSB ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of ...
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Serial interfaces 2 The I C master controller uses just two signals: ● SDA (Serial Data) - bidirectional serial data ● SCL (Serial Clock) - bidirectional serial clock Table 46 lists the GPIO pins used by the SC1 and SC2 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 2 Table 48 master frame segments SCx_TWICTRL1 (1) SC_TWIxxxx START SEND RECV STOP ...
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Serial interfaces receive frame segment is determined with the SC_TWIACK bit in the SCx_TWICTRL2 register. 2 Figure 11 segment transitions Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.5.3 Interrupts master controller interrupts are generated on the following events: ● Bus command (SC_TWISTART/SC_TWISTOP) completed ( transition of SC_TWICMDFIN) ● Character transmitted and slave device responded with NACK ● ...
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Serial interfaces 9.6.1 Setup and configuration The UART baud rate clock is produced by a programmable baud generator starting from the 24 Hz clock: The integer portion of the divisor written to the SC1_UARTPER register and the fractional ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ A UART character frame contains, in sequence: ● The start bit ● The least significant data bit ● The remaining data bits ● If parity is enabled, the parity bit ● The stop bit, or ...
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Serial interfaces Figure 14. RTS/CTS flow control connections UART Transmitter The UART RTS/CTS flow control options are selected by the SC1_UARTFLOW and SC1_UARTAUTO bits in the SC1_UARTCFG register (see SC1_UARTFLOW bit is set, the UART will not start transmitting a ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ offset is 4 characters ahead of the actual overflow at the input to the receive FIFO. Two conditions will clear the error indication: setting the appropriate SC_RXDMARST bit in the SC1_DMACTRL register, or loading the ...
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Serial interfaces ● Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register. ● Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the SCx_DMACTRL register. A DMA buffer's ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) Address offset: 0xA808 (INT_SC1FLAG) and 0xA80C (INT_SC2FLAG) Reset value: Table 53. Serial controller interrupt flag register (INT_SCxFLAG INT_S ...
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Serial interfaces 9.8.3 Serial controller interrupt configuration register (INT_SCxCFG) Address offset: 0xA848 (INT_SC1CFG) and 0xA84C (INT_SC2CFG) Reset value: Table 54. Serial controller interrupt configuration register (INT_SCxCFG INT_S INT_S INT_S INT_S ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.8.4 Serial controller interrupt mode register (SCx_INTMODE) Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE) Reset value: Table 55. Serial controller interrupt mode register (SCx_INTMODE Bit ...
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Serial interfaces 9.9.2 SPI configuration register (SCx_SPICFG) Address offset: 0xC858 (SC1_SPICFG) and 0xC058 (SC2_SPICFG) Reset value: Table 57. SPI configuration register (SCx_SPICFG Reserved Bit 5 SC_SPIRXDRV: Receiver-driven mode selection bit ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.9.3 SPI status register (SCx_SPISTAT) Address offset: 0xC840 (SC1_SPISTAT) and 0xC040 (SC2_SPISTAT) Reset value: Table 58. SPI status register (SCx_SPISTAT Bit 3 SC_SPITXIDLE: This bit ...
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Serial interfaces 9.9.5 Serial clock exponential prescaler register (SCx_RATEEXP) Address offset: 0xC864 (SC1_RATEEXP) and 0xC064 (SC2_RATEEXP) Reset value: Table 60. Serial clock exponential prescaler register (SCx_RATEEXP Bits [3:0] SC_RATEEXP: The ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 2 9.11 control 1 register (SCx_TWICTRL1) Address offset: 0xC84C (SC1_TWICTRL1) and 0xC04C (SC2_TWICTRL1) Reset value: 2 Table 62 control 1 register (SCx_TWICTRL1 ...
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Serial interfaces 9.12 Universal asynchronous receiver / transmitter (UART) registers Refer to the SPI Master mode section for a description of the SCx_DATA register. 9.12.1 UART status register (SC1_UARTSTAT) Address offset: 0xC848 Reset value: Table 64. UART status register (SC1_UARTSTAT) ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.12.2 UART configuration register (SC1_UARTCFG) Address offset: 0xC85C Reset value: Table 65. UART configuration register (SC1_UARTCFG Reserved Bit 6 SC_UARTAUTO: Set this bit to enable ...
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Serial interfaces 9.12.3 UART baud rate period register (SC1_UARTPER) Address offset: 0xC868 Reset value: Table 66. UART baud rate period register (SC1_UARTPER Bits [15:0] SC_UARTPER: The integer part of baud ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.13 DMA channel registers 9.13.1 Serial DMA control register (SCx_DMACTRL) Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL) Reset value: Table 68. Serial DMA control register (SCx_DMACTRL ...
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Serial interfaces 9.13.2 Serial DMA status register (SCx_DMASTAT) Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT) Reset value: Table 69. Serial DMA status register (SCx_DMASTAT SC_RXSSEL Reserved r Bits [12:10] SC_RXSSEL: ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bit 2 This bit is set when DMA transmit buffer A is active. Bit 1 This bit is set when DMA receive buffer B is active. Bit 0 This bit is set when DMA receive ...
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Serial interfaces 9.13.5 Transmit DMA end address register A (SCx_TXENDA) Address offset: 0xC814 (SC1_TXENDA) and 0xC014 (SC2_TXENDA) Reset value: Table 72. Transmit DMA end address register A (SCx_TXENDA Reserved Bits ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.13.8 Receive DMA begin address register A (SCx_RXBEGA) Address offset: 0xC800 (SC1_RXBEGA) and 0xC000 (SC2_RXBEGA) Reset value: Table 75. Receive DMA begin address register A (SCx_RXBEGA ...
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Serial interfaces 9.13.10 Receive DMA end address register A (SCx_RXENDA) Address offset: 0xC804 (SC1_RXENDA) and 0xC004 (SC2_RXENDA) Reset value: Table 77. Receive DMA end address register A (SCx_RXENDA Reserved Bits ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.13.12 Receive DMA count register A (SCx_RXCNTA) Address offset: 0xC820 (SC1_RXCNTA) and 0xC020 (SC2_RXCNTA) Reset value: Table 79. Receive DMA count register A (SCx_RXCNTA Reserved ...
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Serial interfaces 9.13.14 Saved receive DMA count register (SCx_RXCNTSAVED) Address offset: 0xC870 (SC1_RXCNTSAVED) and 0xC070 (SC2_RXCNTSAVED) Reset value: Table 81. Saved receive DMA count register (SCx_RXCNTSAVED Reserved Bits [13:0] SC_RXCNTSAVED: ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 9.13.16 DMA first receive error register B (SCx_RXERRB) Address offset: 0xC838 (SC1_RXERRB) and 0xC038 (SC2_RXERRB) Reset value: Table 83. DMA first receive error register B (SCx_RXERRB ...
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General-purpose timers 10 General-purpose timers Each of the STM32W108's two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 15. General-purpose timer block diagram Note: The internal signals shown in descriptions on page 143 components are interconnected. 10.1 Functional description The timers can optionally use GPIOs in the PA and PB ports for ...
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General-purpose timers The GPIOs that can be used by Timer 1 are fixed, but the GPIOs that can be used as Timer 2 channels can be mapped to either of two pins, as shown in Register (TIM2_OR) has four single ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Note: When the STM32W108 enters debug mode and the ARM® Cortex-M3 core is halted, the counters continue to run normally. Prescaler The prescaler can divide the counter clock frequency by power of two from 1 ...
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General-purpose timers When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_USR is 1) and the following registers are updated: ● The buffer of the prescaler is reloaded with the buffer ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 19. Counter timing diagram, update event when TIM_ARBE = 0 (TIMx_ARR not buffered) Figure 20. Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-counting mode In down-counting mode, the counter counts ...
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General-purpose timers reload value, whereas the prescalar's counter restarts from 0, but the prescale rate doesn't change. In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates an update event, but without setting ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written updated by ...
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General-purpose timers Figure 24. Counter timing diagram, update event with TIM_ARBE = 1 (counter underflow) Figure 25. Counter timing diagram, update event with TIM_ARBE = 1 (counter overflow) 120/220 STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Doc ID 16252 Rev 9 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 10.1.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (PCLK) ● External clock mode 1: external input pin (TIy) ● External clock mode 2: external trigger input ...
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General-purpose timers Figure 27. TI2 external clock connection example For example, to configure the up-counter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ External clock source mode 2 This mode is selected by writing TIM_ECE = 1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The ...
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General-purpose timers Figure 30. Control circuit in external clock mode 2 10.1.4 Capture/compare channels Each capture/compare channel is built around a capture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 32. Capture/compare channel 1 main circuit Figure 33. Output stage of capture/compare channel (channel 1) The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access the ...
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General-purpose timers cleared by software writing its bit or reading the captured data stored in the TIMx_CCRy register. To clear the INT_TIMMISSCCyIF bit, write it. The following example shows how to capture the counter ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the TIMx_CCR2 register of the PWM applied on TI1, use the following procedure depending on CK_INT frequency and prescaler value: ...
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General-purpose timers The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the TIMx_CCMR1 register. The comparison between the TIMx_CCRy shadow register and the counter is still performed and allows the INT_TIMxCCRyIF flag to be ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 35. Output compare mode, toggle on OC1 10.1.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register, and a duty ...
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General-purpose timers PWM edge-aligned mode: up-counting configuration Up-counting is active when the TIM_DIR bit in the TIMx_CR1 register is low. Refer to counting mode on page The following example uses PWM mode 1. The reference PWM signal OCyREF is high ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 37 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR = 8, ● PWM mode is the PWM mode 1, ● The output compare flag is set when the counter counts down ...
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General-purpose timers ● The direction is not updated the value written to the counter that is greater than the auto-reload value (TIMx_CNT > TIMx_ARR). For example, if the counter was counting up, it continues to count up. ● The direction ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ For example, to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a rising edge is detected on the TI2 input pin, using TI2FP2 ...
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General-purpose timers filtered and not inverted.) The sequence of transitions of the two inputs is evaluated, and generates count pulses as well as the direction signal. Depending on the sequence, the counter counts up or down, and hardware modifies the ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 39. Example of counter operation in encoder interface mode Figure 40 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except TIM_CC1P = 1). Figure 40. Example of ...
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General-purpose timers The XOR output can be used with all the timer input functions such as trigger or input capture especially useful to interface to Hall effect sensors. 10.1.13 Timers and external trigger synchronization The timers can be ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Slave mode: Gated mode In Gated mode the counter is enabled depending on the level of a selected input. In the following example, the up-counter counts only when the TI1 input is low: ● Configure ...
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General-purpose timers The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on the TI2 input. Figure 43. Control circuit in Trigger mode Slave mode: External clock mode 2 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 44. Control circuit in External clock mode 2 + Trigger mode 10.1.14 Timer synchronization The two timers can be linked together internally for timer synchronization or chaining. A timer configured in Master mode can ...
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General-purpose timers Using one timer to enable the other timer In this example, the enable of Timer 2 is controlled with the output compare 1 of Timer 1. Refer to Figure 45 OC1REF of Timer 1 is high. Both counter ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ ● Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing 1 ...
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General-purpose timers Figure 48. Triggering timer 2 with update of Timer the previous example, both counters can be initialized before starting counting. Figure 47 shows the behavior with the same configuration shown in mode instead of gated ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ ● Configure the Timer 1 in master/slave mode by writing TIM_MSM = 1 (TIM1_SMCR register). ● Configure Timer 2 to get the input trigger from Timer 1 (TIM_TS = 000 in the TIM2_SMCR register). ● ...
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General-purpose timers Table 87. Timer signal descriptions (continued) Signal ICyPS ITR0 OCy OCyREF PCLK TIy TIyFPy TIMxCy TIMxCLK TIMxMSK TRGI 10.2 Interrupts Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority. Writing 1 to the INT_TIMx bit ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 10.3 General-purpose timer (1 and 2) registers 10.3.1 Timer x control register 1 (TIMx_CR1) Address offset: 0xE000 (TIM1) and 0xF000 (TIM2) Reset value: Table 88. Timer x control register 1 (TIMx_CR1 ...
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General-purpose timers Bit 1 TIM_UDIS: Update Disable 0: An update event is generated as soon as a counter overflow occurs, a software update is generated hardware reset is generated by the slave mode controller. Shadow registers are then ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bits [6:4] TIM_MMS: Master Mode Selection This selects the information to be sent in master mode to a slave timer for synchronization using the trigger output (TRGO). 000: Reset - the TIM_UG bit in the ...
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General-purpose timers Bit 14 TIM_ECE: External Clock Enable This bit enables external clock mode 2. 0: External clock mode 2 disabled. 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bits [2:0] TIM_SMS: Slave Mode Selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. If TIM_CEN ...
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General-purpose timers Bit 6 TIM_TG: Trigger Generation 0: Does nothing. 1: Sets the TIM_TIF flag in the INT_TIMxFLAG register. Bit 4 TIM_CC4G: Capture/Compare 4 Generation 0: Does nothing CC4 configured as output channel: The TIM_CC4IF flag is set. ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 10.3.5 Timer x capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0xE018 (TIM1) and 0xF018 (TIM2) Reset value: Table 92. Timer x capture/compare mode register 1 (TIMx_CCMR1 ...
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General-purpose timers Bit 10 TIM_OC2FE: Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0) This bit speeds the effect of an event on the trigger in input on the OC2 output. 0: OC2 behaves normally depending on the ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bits [1:0] TIM_CC1S: Capture / Compare 1 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an ...
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General-purpose timers Bits [14:12] TIM_OC4M: Output Compare 4 Mode. (Applies only if TIM_CC4S = 0 Define the behavior of the output reference signal OC4REF from which OC4 derives. OC4REF is active high whereas OC4’s active level depends on the TIM_CC4P ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bits [15:12] TIM_IC4F: Input Capture 1 Filter. (Applies only if TIM_CC4S > 0) This defines the frequency used to sample the TI4 input, f filter applied to TI4. The digital filter requires N consecutive samples ...
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General-purpose timers Bits [1:0] TIM_CC3S: Capture / Compare 3 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bit 5 TIM_CC2P Refer to the CC4P description above. Bit 4 TIM_CC2E Refer to the CC43 description above. Bit 1 TIM_CC1P Refer to the CC4P description above. Bit 0 TIM_CC1E Refer to the CC4E description ...
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General-purpose timers 10.3.10 Timer x auto-reload register (TIMx_ARR) Address offset: 0xE02C (TIM1) and 0xF02C (TIM2) Reset value: Table 97. Timer x auto-reload register (TIMx_ARR Bits [15:0] TIM_ARR: Auto-reload value TIM_ARR ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2) Address offset: 0xE038 (TIM1) and 0xF038 (TIM2) Reset value: Table 99. Timer x capture/compare 2 register (TIMx_CCR2 Bits ...
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General-purpose timers 10.3.15 Timer 1 option register (TIM1_OR) Address offset: 0xE050 Reset value: Table 102. Timer 1 option register (TIM1_OR Bit 3 TIM_ORRSVD Reserved: this bit must always be set ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Bit 3 TIM_ORRSVD Reserved: this bit must always be set to 0. Bit 2 TIM_CLKMSKEN Enables TIM2MSK when TIM2CLK is selected as the external trigger TIM2MSK not used TIM2CLK is ANDed ...
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General-purpose timers Bits [12:9] INT_TIMRSVD: May change during normal operation. Bit 6 INT_TIMTIF: Trigger interrupt. Bit 4 INT_TIMCC4IF: Capture or compare 4 interrupt pending. Bit 3 INT_TIMCC3IF: Capture or compare 3 interrupt pending. Bit 2 INT_TIMCC2IF: Capture or compare 2 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter 11 Analog-to-digital converter The STM32W108 analog-to-digital converter (ADC first-order sigma-delta converter with the following features: ● Resolution bits ● Sample times as fast as 5.33 µs (188 ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.1 Functional description 11.1.1 Setup and configuration To use the ADC follow this procedure, described in more detail in the next sections: ● Configure any GPIO pins to be used by the ADC ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter 11.1.4 Offset/gain correction When a conversion is complete, the 16-bit converted data is processed by offset/gain correction logic: ● The basic ADC conversion result is added to the 16-bit signed (two’s complement) value ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.1.6 ADC configuration register The ADC configuration register (ADC_CFG) sets up most of the ADC operating parameters. Input The analog input of the ADC can be chosen from various sources. The analog input ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter Table 109. Typical ADC input configurations (continued) ADC P input ADC5 GND VREF VDD_PADSA/2 Input range ADC inputs can be routed through input buffers to expand the input voltage range. The input buffers ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 110. ADC sample times (continued) Sample ADC_PERIOD clocks 6 7 Note: ADC sample timing is the same whether the STM32W108 is using the 24 MHz crystal oscillator or the 12 MHz high-speed ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter To convert multiple inputs using this approach, repeat Steps 4 through 6, loading the desired input configurations to ADC_CFG in Step 5. If the inputs can use the same offset/gain correction, just repeat ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.2 Interrupts The ADC has its own ARM ADC interrupt is enabled by writing the INT_ADC bit to the INT_CFGSET register, and cleared by writing the INT_ADC bit to the INT_CFGCLR register. page ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter 11.3 Analog-to-digital converter (ADC) registers 11.3.1 ADC configuration register (ADC_CFG) Address offset: 0xD004 Reset value: Table 112. ADC configuration register (ADC_CFG ADC_ ADC_ ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.3.2 ADC offset register (ADC_OFFSET) Address offset: 0xD008 Reset value: Table 113. ADC offset register (ADC_OFFSET Bits [15:0] ADC_OFFSET_FIELD: 16-bit signed offset added ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter 11.3.4 ADC DMA configuration register (ADC_DMACFG) Address offset: 0xD010 Reset value: Table 115. ADC DMA configuration register (ADC_DMACFG Bit 4 ADC_DMARST: Write 1 ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.3.6 ADC DMA begin address register (ADC_DMABEG) Address offset: 0xD018 Reset value: Table 117. ADC DMA begin address register (ADC_DMABEG Reserved Bits [13:0] ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter Table 118. ADC DMA buffer size register (ADC_DMASIZE Reserved Bits [12:0] ADC_DMASIZE_FIELD: ADC buffer size. This is the number of 16-bit ADC conversion ...
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Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 11.3.10 ADC interrupt flag register (INT_ADCFLAG) Address offset: 0xA810 Reset value: Table 121. ADC interrupt flag register (INT_ADCFLAG Bit 4 INT_ADCOVF: DMA buffer ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 12 Interrupts The STM32W108's interrupt system is composed of two parts: a standard ARM® Cortex- M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an Event Manager (EM) that provides second level ...
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Interrupts Table 123. NVIC exception table (continued) Exception NMI Hard Fault Memory Fault Bus Fault Usage Fault - SVCall Debug Monitor - PendSV SysTick Timer 1 Timer 2 Management Baseband Sleep Timer Serial Controller 1 Serial Controller 2 Security MAC ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ The NVIC also contains a software-configurable interrupt prioritization mechanism. The Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are not software-configurable. All other exceptions can be assigned a ...
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Interrupts 12.1.2 Faults Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these four, three of the faults (Hard Fault, Memory Fault, and Usage Fault) are all standard ARM® Cortex-M3 ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Figure 52. Peripheral interrupts block diagram peripheral interrupt instance OR AND S source interrupt events The description of each peripheral's interrupt configuration and flag registers can be found in the chapters of this datasheet describing ...
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Interrupts facilitate software detection of such problems. The INT_MISS register is "acknowledged" in the same way as the INT_periphFLAG register-by writing a 1 into the corresponding bit to be cleared. Table 124 provides a map of all peripheral interrupts. This ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 124. NVIC and EM peripheral interrupt map NVIC Interrupt (top level) 16 INT_DEBUG 15 INT_IRQD 14 INT_IRQC 13 INT_IRQB 12 INT_IRQA 11 INT_ADC 10 INT_MACRX 9 INT_MACTX 8 INT_MACTMR 7 INT_SEC 6 INT_SC2 EM ...
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Interrupts 12.3 Nested vectored interrupt controller (NVIC) interrupts 12.3.1 Top-level set interrupts configuration register (INT_CFGSET) Address: 0xE000E100 Reset value: Table 125. Top-level set interrupts configuration register (INT_CFGSET INT_IR INT_IR INT_IR ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 12.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) Address: 0xE000E180 Reset value: Table 126. Top-level clear interrupts configuration register (INT_CFGCLR INT_I INT_I INT_I INT_I INT_A RQD ...
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Interrupts 12.3.3 Top-level set interrupts pending register (INT_PENDSET) Address: 0xE000E200 Reset value: Table 127. Top-level set interrupts pending register (INT_PENDSET INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA DC ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 12.3.4 Top-level clear interrupts pending register (INT_PENDCLR) Address: 0xE000E280 Reset value: Table 128. Top-level clear interrupts pending register (INT_PENDCLR INT_I INT_I INT_I INT_I INT_A RQD ...
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Interrupts 12.3.5 Top-level active interrupts register (INT_ACTIVE) Address: 0xE000E300 Reset value: Table 129. Top-level active interrupts register (INT_ACTIVE INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 12.3.6 Top-level missed interrupts register (INT_MISS) Address: 0x4000 A820 Reset value: Table 130. Top-level missed interrupts register (INT_MISS INT_M INT_M INT_M INT_M INT_M ISSIR ISSIR ...
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Interrupts 12.3.7 Auxiliary fault status register (SCS_AFSR) Address: Reset value: Table 131. Auxiliary fault status register (SCS_AFSR Bit 3 WRONGSIZE A bus fault resulted from an 8-bit or 16-bit read ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 13 Debug support The STM32W108 includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and programming interface of the STM32W108. The SWJ gives debug tools access to the internal ...
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Debug support 13.1 STM32W108 JTAG TAP connection The STM32W108 MCU integrates two serially-connected JTAG TAPs in the following order; the TMC TAP dedicated for Test (IR is 4-bit wide) and the Cortex™-M3 TAP (IR is 4-bit wide). To access the ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 14 Electrical characteristics 14.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 14.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ...
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Electrical characteristics 14.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 133: Current permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ 14.3 Operating conditions 14.3.1 General operating conditions Table 135. General operating conditions Symbol – Regulator input voltage (VDD_PADS) Analog and memory input voltage (VDD_24MHZ, – VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_MEM, VDD_PRE, and VDD_SYNTH) – Core ...
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Electrical characteristics The POR LVcore and POR LVmem reset sources are merged to provide a single reset source, POR LV, to the Reset Generation module, since the detection of either event needs to reset the same system modules. NRST pin ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each ...
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Electrical characteristics Table 142. ADC module key parameters for 1 MHz sampling Parameter THD (dB) Single-Ended Differential ENOB (from SNR) Single-Ended Differential ENOB (from SINAD) Single-Ended Differential Equivalent ADC Bits 1. INL and DNL are referenced to a LSB of ...
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STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Table 143. ADC module key parameters for input buffer disabled and 6 MHz sampling Parameter SDFR (dB) Single-Ended Differential THD (dB) Single-Ended Differential ENOB (from SNR) Single-Ended Differential ENOB (from SINAD) Single-Ended Differential Equivalent ADC ...
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Electrical characteristics Table 144 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling rate of 6 MHz. ADC_HVSELP and ADC_HVSELN are programmed enable the input buffer. The single-ended measurements were ...