STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 176

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

Analog-to-digital converter STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
11.3.10
Table 121. ADC interrupt flag register (INT_ADCFLAG)
11.3.11
Table 122. ADC interrupt configuration register (INT_ADCCFG)
176/220
31
15
31
15
30
14
30
14
ADC interrupt flag register (INT_ADCFLAG)
Address offset: 0xA810
Reset value:
ADC interrupt configuration register (INT_ADCCFG)
Address offset: 0xA850
Reset value:
29
13
29
13
28
12
28
12
Bit 4 INT_ADCOVF: DMA buffer overflow interrupt pending.
Bit 3 INT_ADCSAT: Gain correction saturation interrupt pending.
Bit 2 INT_ADCULDFULL: DMA buffer full interrupt pending.
Bit 1 INT_ADCULDHALF: DMA buffer half full interrupt pending.
Bit 0 Reserved: this bit should always be set to 1.
Bit 4 INT_ADCOVF: DMA buffer overflow interrupt enable.
Bit 3 INT_ADCSAT: Gain correction saturation interrupt enable.
Bit 2 INT_ADCULDFULL: DMA buffer full interrupt enable.
Bit 1 INT_ADCULDHALF: DMA buffer half full interrupt enable.
Bit 0 ST Reserved: this bit must always be set to 0.
27
11
27
11
0x0000 0000
0x0000 0000
Reserved
Reserved
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 9
24
24
8
8
Reserved
Reserved
23
23
7
7
22
22
6
6
21
21
5
5
INT_A
DCOV
INT_A
DCOV
20
rw
20
rw
F
F
4
4
DCSAT
DCSAT
INT_A
INT_A
19
rw
19
rw
3
3
DFULL
DFULL
INT_A
INT_A
DCUL
DCUL
18
18
rw
rw
2
2
DHALF
DHALF
INT_A
INT_A
DCUL
DCUL
17
17
rw
rw
1
1
ST Re-
ST Re-
served
served
16
rw
16
0
0