STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 181

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
Figure 52. Peripheral interrupts block diagram
The description of each peripheral's interrupt configuration and flag registers can be found
in the chapters of this datasheet describing each peripheral.
Given a peripheral, 'periph', the Event Manager registers (INT_periphCFG and
INT_periphFLAG) follow the form:
●
●
If a bit in the INT_periphCFG register is set after the corresponding bit in the
INT_periphFLAG register is set then the second-level interrupt propagates into the top level
interrupts. The interrupt flags (signals) from the second-level interrupts into the top-level
interrupts are level-sensitive. If a top-level NVIC interrupt is driven by a second-level EM
interrupt, then the top-level NVIC interrupt cannot be cleared until all second-level EM
interrupts are cleared.
The INT_periphFLAG register bits are designed to remain set if the second-level interrupt
event re-occurs at the same moment as the INT_periphFLAG register bit is being cleared.
This ensures the re-occurring second-level interrupt event is not missed.
If another enabled second-level interrupt event of the same type occurs before the first
interrupt event is cleared, the second interrupt event is lost because no counting or queuing
is used. However, this condition is detected and stored in the top-level INT_MISS register to
INT_periphCFG enables and disables second-level interrupts. Writing 1 to a bit in the
INT_periphCFG register enables the second-level interrupt. Writing 0 to a bit in the
INT_periphCFG register disables it. The INT_periphCFG register behaves like a mask,
and is responsible for allowing the INT_periphFLAG bits to propagate into the top level
NVIC interrupts.
INT_periphFLAG indicates second-level interrupts that have occurred. Writing 1 to a bit
in a INT_periphFLAG register clears the second-level interrupt. Writing 0 to any bit in
the INT_periphFLAG register is ineffective. The INT_periphFLAG register is always
active and may be set or cleared at any time, meaning if any second-level interrupt
occurs, then the corresponding bit in the INT_periphFLAG register is set regardless of
the state of INT_periphCFG.
source interrupt events
OR
AND
peripheral interrupt instance
S
latch
OR
Q
AND
R
INT_periphFLAG
write 1
read
INT_periphCFG
Doc ID 16252 Rev 9
interrupts from all peripherals
interrupts into NVIC /CPU
OR
S
S
latch
latch
Q
Q
AND
R
R
S
latch
Q
R
write 1
write 1
write 1
write 1
write 1
INT_PENDCLR
INT_PENDSET
INT_CFGCLR
INT_CFGSET
read
read
INT_MISS
read
Interrupts
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