STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 178

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

Interrupts
178/220
Table 123. NVIC exception table (continued)
Serial Controller 1
Serial Controller 2
Debug Monitor
MAC Transmit
Memory Fault
MAC Receive
Management
Sleep Timer
Usage Fault
MAC Timer
Exception
Hard Fault
Baseband
Bus Fault
PendSV
Security
SysTick
Timer 1
Timer 2
SVCall
Debug
IRQA
IRQB
IRQC
IRQD
ADC
NMI
-
-
STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
Position
7-10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
Cannot be stopped or preempted by any exception but reset.
Asynchronous.
All classes of fault, when the fault cannot activate because of priority
or the Configurable Fault handler has been disabled. Synchronous.
MPU mismatch, including access violation and no match.
Synchronous.
Pre-fetch, memory access, and other address/memory-related faults.
Synchronous when precise and asynchronous when imprecise.
Usage fault, such as 'undefined instruction executed' or 'illegal state
transition attempt'. Synchronous.
Reserved.
System service call with SVC instruction. Synchronous.
Debug monitor, when not halting. Synchronous, but only active when
enabled. It does not activate if lower priority than the current
activation.
Reserved.
Pendable request for system service. Asynchronous and only pended
by software.
System tick timer has fired. Asynchronous.
Timer 1 peripheral interrupt.
Timer 2 peripheral interrupt.
Management peripheral interrupt.
Baseband peripheral interrupt.
Sleep Timer peripheral interrupt.
Serial Controller 1 peripheral interrupt.
Serial Controller 2 peripheral interrupt.
Security peripheral interrupt.
MAC Timer peripheral interrupt.
MAC Transmit peripheral interrupt.
MAC Receive peripheral interrupt.
ADC peripheral interrupt.
IRQA peripheral interrupt.
IRQB peripheral interrupt.
IRQC peripheral interrupt.
IRQD peripheral interrupt.
Debug peripheral interrupt.
Doc ID 16252 Rev 9
Description