STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 163

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter
11
Note:
Note:
Analog-to-digital converter
The STM32W108 analog-to-digital converter (ADC) is a first-order sigma-delta converter
with the following features:
●
●
●
●
●
●
●
Figure 51
Figure 51. ADC block diagram
While the ADC Module supports both single-ended and differential inputs, the ADC input
stage always operates in differential mode. Single-ended conversions are performed by
connecting one of the differential inputs to VREF/2 while fully differential operation uses two
external inputs.
This note only applies to STM32W108xB. In high voltage mode, input buffers (with 0.25 gain
only) may experience long term drift of its input offset voltage that affects ADC accuracy. In
these cases, only the 1.2V input range mode of the ADC should be used. If measurement of
signals >1.2V is required, then external attenuation should be added.
For STM32W108CC and STM32108CZ, high voltage mode is supported only in single
mode. It is also required by the software to periodically set to 1 bit ADC_HVSELN in the
register ADC_CFG.
Resolution of up to 12 bits
Sample times as fast as 5.33 µs (188 kHz)
Differential and single-ended conversions from six external and four internal sources
Two voltage ranges (differential): -VREF to +VREF, and –VDD_PADS to +VDD_PADS
Choice of internal or external VREF: internal VREF may be output
Digital offset and gain correction
Dedicated DMA channel with one-shot and continuous operating modes
shows the basic ADC structure.
Doc ID 16252 Rev 9
163/220