STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 24

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

Pinout and pin description STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
Table 2.
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Package
Pin no.
48-Pin
34
35
36
37
Package
Pin no.
40-Pin
Pin descriptions (continued)
29
30
PC3
JTDI
PC4
JTMS
SWDIO
PB0
VREF
VREF
IRQA
TRACECLK
(see also Pin
25)
TIM1CLK
TIM2MSK
VDD_PADS
Signal
Direction
Analog O
Analog I
Power
I/O
I/O
I/O
I/O
O
I
I
I
I
I
Doc ID 16252 Rev 9
Digital I/O
Either Enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description)
JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Internal pull-up is enabled
Digital I/O
Enable with GPIO_DBGCFG[5]
JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing NRST low
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
Digital I/O
ADC reference output.
Enable analog function with GPIO_PBCFGL[3:0].
ADC reference input.
Enable analog function with GPIO_PBCFGL[3:0].
Enable reference output with an ST system function.
External interrupt source A.
Synchronous CPU trace clock.
Enable trace interface in ARM core.
Select alternate output function with GPIO_PBCFGL[3:0].
Timer 1 external clock input.
Timer 2 external clock mask input.
Pads supply (2.1 to 3.6 V).
Description