STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 25

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Pinout and pin description
Table 2.
Package
Pin no.
48-Pin
38
39
40
41
Package
Pin no.
40-Pin
Pin descriptions (continued)
31
32
33
34
PC1
ADC3
SWO
(see also Pin
33)
TRACEDATA0
VDD_MEM
PC0
JRST
IRQD
TRACEDATA1
PB7
ADC2
IRQC
TIM1_CH2
Signal
(1)
(1)
Direction
Analog
current
current
Analog
Power
High
High
I/O
I/O
I/O
O
O
O
O
I
I
I
I
Doc ID 16252 Rev 9
Digital I/O
ADC Input 3
Enable analog function with GPIO_PCCFGL[7:4]
Serial Wire Output asynchronous trace output to debugger
Select asynchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
Synchronous CPU trace data bit 0
Select 1-, 2- or 4-wire synchronous trace interface in ARM
core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
1.8 V supply (flash, RAM)
Digital I/O
Either enable with GPIO_DBGCFG[5],
or enable Serial Wire mode (see JTMS description, Pin 35)
and disable TRACEDATA1
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS
description) and TRACEDATA1 is disabled
Internal pull-up is enabled
Default external interrupt source D
Synchronous CPU trace data bit 1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[3:0]
Digital I/O
ADC Input 2
Enable analog function with GPIO_PBCFGH[15:12]
Default external interrupt source C
Timer 1 channel 2 output
Enable timer output in TIM1_CCER
Select alternate output function with GPIO_PBCFGH[15:12]
Timer 1 channel 2 input (Cannot be remapped)
Description
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