STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 173

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ Analog-to-digital converter
11.3.4
Table 115. ADC DMA configuration register (ADC_DMACFG)
11.3.5
Table 116. ADC DMA status register (ADC_DMASTAT)
31
15
31
15
30
14
30
14
ADC DMA configuration register (ADC_DMACFG)
Address offset: 0xD010
Reset value:
ADC DMA status register (ADC_DMASTAT)
Address offset: 0xD014
Reset value:
Bit 4 ADC_DMARST: Write 1 to reset the ADC DMA. This bit auto-clears.
Bit 1 ADC_DMAAUTOWRAP: Selects DMA mode.
Bit 0 ADC_DMALOAD: Loads the DMA buffer.
Bit 1 ADC_DMAOVF: DMA overflow: occurs when an ADC result is ready and the DMA is not active.
Bit 0 ADC_DMAACT: DMA status: reads 1 if DMA is active.
29
13
29
13
0: Linear mode, the DMA stops when the buffer is full.
1: Auto-wrap mode, the DMA output wraps back to the start when the buffer is full.
Write 1 to start DMA (writing 0 has no effect). Cleared when DMA starts or is reset.
Cleared by DMA reset.
28
12
28
12
27
11
27
11
0x0000 0000
0x0000 0000
Reserved
26
10
26
10
25
25
9
9
Reserved
Doc ID 16252 Rev 9
24
24
8
8
Reserved
Reserved
23
23
7
7
22
22
6
6
21
21
5
5
DMAR
ADC_
ST
20
20
w
4
4
19
19
3
3
Reserved
18
18
2
2
MAOVF
UTOW
ADC_D
DMAA
ADC_
RAP
17
17
rw
1
1
r
173/220
MAACT
ADC_D
ADC_
DMAL
OAD
16
rw
16
0
0
r