STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 45

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
6.4.3
6.4.4
Table 9.
Table 10.
31
15
31
15
30
14
30
14
Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see
switching on page
Slow timers (Watchdog and Sleeptimer) control and status registers
These registers are powered from the always-on power domain.
All registers are only writable when in System mode
Watchdog general control register (WDOG_CFG)
Register bits for general top level chip functions and protection.
Watchdog bits can only be written after first writing the appropriate code to the
WDOG_CTRL register.
Address:
Reset value:
Watchdog general control register (WDOG_CFG)
Watchdog control register (WDOG_CTRL)
Requires magic number write to arm the watchdog enable or disable function.
Address:
Reset value:
Watchdog control register (WDOG_CTRL)
Bit 1 WDOG_DIS: Watchdog disable
Bit 0 WDOG_EN: Watchdog enable
29
13
29
13
28
12
28
12
27
11
27
11
0x4000 6000
0x0000 0002
0x4000 6004
0x0000 0000
42).
26
10
26
10
25
25
9
9
Reserved
Doc ID 16252 Rev 9
24
24
WDOG_CTRL
8
8
Reserved
Reserved
w
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
Section 6.3.5: Clock
System modules
18
18
2
2
WDOG
_DIS
17
17
rw
1
1
45/220
WDOG
_EN
16
rw
16
0
0