STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 129

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108HB, STM32W108CC, STM32W108CB and STM32W108CZ
10.1.9
Figure 35. Output compare mode, toggle on OC1
PWM mode
Pulse width modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register, and a duty cycle determined by the value of the
TIMx_CCRy register.
PWM mode can be selected independently on each channel (one PWM per OCy output) by
writing 110 (PWM mode 1) or 111 (PWM mode 2) in the TIM_OCyM bits in the
TIMx_CCMR1 register. The corresponding buffer register must be enabled by setting the
TIM_OCyBE bit in the TIMx_CCMR1 register. Finally, in up-counting or center-aligned mode
the auto-reload buffer register must be enabled by setting the TIM_ARBE bit in the
TIMx_CR1 register.
Because the buffer registers are only transferred to the shadow registers when an update
event occurs, before starting the counter initialize all the registers by setting the TIM_UG bit
in the TIMx_EGR register.
OCy polarity is software programmable using the TIM_CCyP bit in the TIMx_CCER register.
It can be programmed as active high or active low. OCy output is enabled by the TIM_CCyE
bit in the TIMx_CCER register. Refer to the TIMx_CCER register description in the
Registers section for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRy are always compared to determine
whether TIMx_CCRy ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRy,depending on the direction of
the counter. The OCyREF signal is asserted only:
●
●
This allows software to force a PWM output to a particular state while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the TIM_CMS bits in the TIMx_CR1 register.
When the result of the comparison changes, or
When the output compare mode (TIM_OCyM bits in the TIMx_CCMR1 register)
switches from the "frozen" configuration (no comparison, TIM_OCyM = 000) to one of
the PWM modes (TIM_OCyM = 110 or 111).
Doc ID 16252 Rev 9
General-purpose timers
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